Patents by Inventor Udayan Dasgupta
Udayan Dasgupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140247171Abstract: A method, comprising: receiving an analog input; determining an upper outer rail and a lower outer rail as polling values to be used by voltage comparators; blanking at least three comparators; determining which two of the at least three comparators are closest to the input analog voltage levels; defining the two comparators which are closest to the analog input signal to be the next comparators of the next sampling process; assigning a remaining comparator at a voltage level in between the new top and bottom voltage levels; enabling the outer rails, but blanking the inner rail; progressively narrowing down the voltage range spanned by the two outer comparators; and generating a 2-tuple value of an asynchronous voltage comparator crossing.Type: ApplicationFiled: February 28, 2014Publication date: September 4, 2014Inventors: Janakiraman S., Udayan Dasgupta, Ganesan Thiagarajan, Abhijit A. Patki, Madhulatha Bonu, Venugopal Gopinathan
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Publication number: 20140247172Abstract: A snapout calculator, and wherein the snapout calculator determines where the reference levels for the various comparators shall be placed after each asynchronous sample is generated.Type: ApplicationFiled: February 28, 2014Publication date: September 4, 2014Inventors: Udayan Dasgupta, Abhijit A. Patki, Ganesan Thiagarajan
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Patent number: 8760329Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. If the comparison result remains substantially the same for a predetermined interval, an ADC is enabled to generate a second comparison result at a sampling instant. A second time stamp that corresponds to the sampling instant is generated. The second comparison result and a second time stamp corresponding to the first comparison result are registered, and a second portion of the digital signal is generated from the second comparison result.Type: GrantFiled: August 30, 2012Date of Patent: June 24, 2014Assignee: Texas Instruments IncorporatedInventors: Ganesan Thiagarajan, Udayan Dasgupta, Venugopal Gopinathan
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Patent number: 8754797Abstract: An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.Type: GrantFiled: August 30, 2012Date of Patent: June 17, 2014Assignee: Texas Instruments IncorporatedInventors: Venugopal Gopinathan, Udayan Dasgupta, Ganesan Thiagarajan
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Publication number: 20140062734Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. If the comparison result remains substantially the same for a predetermined interval, an ADC is enabled to generate a second comparison result at a sampling instant. A second time stamp that corresponds to the sampling instant is generated. The second comparison result and a second time stamp corresponding to the first comparison result are registered, and a second portion of the digital signal is generated from the second comparison result.Type: ApplicationFiled: August 30, 2012Publication date: March 6, 2014Applicant: Texas Instruments IncorporatedInventors: Ganesan Thiagarajan, Udayan Dasgupta, Venugopal Gopinathan
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Publication number: 20140062751Abstract: An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.Type: ApplicationFiled: August 30, 2012Publication date: March 6, 2014Applicant: Texas Instruments IncorporatedInventors: Venugopal Gopinathan, Udayan Dasgupta, Ganesan Thiagarajan
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Publication number: 20140062735Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result.Type: ApplicationFiled: August 30, 2012Publication date: March 6, 2014Applicant: Texas Instruments IncorporatedInventors: Udayan Dasgupta, Ganesan Thiagarajan, Venugopal Gopinathan
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Publication number: 20120184855Abstract: Methods for color Doppler imaging in an ultrasound imaging system are disclosed herein. Ultrasound radio frequency RF data is demodulated using a nested processing loop including an inner loop and an outer loop. A plurality of Wall filter coefficients are fetched from ultrasound imaging system memory in a single memory access cycle. The plurality Wall filter coefficients are applied to a plurality of complex ultrasound data values in a single execution cycle. The Wall filtered ultrasound data are provided to a flow estimator.Type: ApplicationFiled: March 28, 2012Publication date: July 19, 2012Applicant: Texas Instruments IncorporatedInventors: Udayan DASGUPTA, David P. MAGEE, Murtaza ALI
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Publication number: 20120183196Abstract: A system for processing real-time fluoroscopy image sequences. A first image frame is loaded into an upper level memory of a hierarchical memory system that is coupled to at least one processing core. The first image frame is processed with an object detection filter to form a likelihood image frame. The first image frame and the likelihood image frame is spatially filtered using a spatial filter look up table (LUT) stored in an L1 level memory of the processing core. The likelihood image frame is temporally filtering using a temporal filter LUT stored in the L1 level memory.Type: ApplicationFiled: January 18, 2012Publication date: July 19, 2012Inventors: Udayan Dasgupta, Murtaza Ali
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Publication number: 20120184856Abstract: Systems for color Doppler imaging in an ultrasound imaging system are disclosed herein. An ultrasound imaging system includes color Doppler imaging circuitry. The color Doppler imaging circuitry is configured to estimate flow parameters. The imaging circuitry includes a radio frequency (“RF”) demodulator configured to produce in-phase and quadrature components of an ultra-sound data vector. The RF demodulator includes a table in memory that stores interleaved sine and cosine values. The RF demodulator maintains an index value for the table having higher precision than is used to index the table. The RF demodulator rounds the index value for each access of the table. Each table access retrieves a sine value and a cosine value.Type: ApplicationFiled: March 28, 2012Publication date: July 19, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Udayan Dasgupta, David P. Magee, Murtaza Ali
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Publication number: 20100211761Abstract: In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. A vector math instruction decoded by the instruction decode unit causes input vectors and output vectors to be aligned with a maximum boundary of the register set and causes parallel operations by the work units.Type: ApplicationFiled: February 18, 2010Publication date: August 19, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Udayan DASGUPTA
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Publication number: 20100004542Abstract: Systems and methods for color Doppler imaging in an ultrasound imaging system are disclosed herein. An ultrasound imaging system includes color Doppler imaging circuitry. The color Doppler imaging circuitry is configured to estimate flow parameters. The imaging circuitry includes a radio frequency (“RF”) demodulator configured to produce in-phase and quadrature components of an ultra-sound data vector. The RF demodulator includes a table in memory that stores interleaved sine and cosine values. The RF demodulator maintains an index value for the table having higher precision than is used to index the table. The RF demodulator rounds the index value for each access of the table. Each table access retrieves a sine value and a cosine value.Type: ApplicationFiled: June 24, 2009Publication date: January 7, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Udayan DASGUPTA, David P. MAGEE, Murtaza ALI
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Publication number: 20090175234Abstract: A method of performing wireless communications. The method comprises, at a transmitting station, encoding a plurality of symbols into a frame. The method further comprises, from the transmitting station, transmitting the frame via a wireless communication to a receiving station. The frame comprises a plurality of sub-frames, wherein a first sub-frame in the plurality of sub-frames consists of a first number of symbols and a second sub-frame in the plurality of sub-frames consists of a second number of symbols. Finally, the first number differs from the second number.Type: ApplicationFiled: January 8, 2009Publication date: July 9, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Udayan Dasgupta, Muhammad Zubair Ikram, David Patrick Magee
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Patent number: 7555049Abstract: A client premises digital subscriber line (DSL) modem having multi-mode capability is disclosed. In initialization, the modem estimates whether channel conditions are such that digital processing of the received data according to a lower data rate DSL standard, such as ADSL2, may result in a higher effective data rate than receipt and processing according to a higher data rate DSL standard, such as ADSL2+. If so, the DSL modem configures itself, such as by configuring its filter characteristics and sampling frequency, to receive and process data according to the lower data rate DSL standard; the transmitting modem, for example at a central office or service area interface, may continue to operate according to the higher data rate standard (with its bit loading corresponding to a subset of subchannels). The receiving DSL modem processes the payload data according to the lower standard, while processing control messages according to the higher standard.Type: GrantFiled: September 6, 2005Date of Patent: June 30, 2009Assignee: Texas Instruments IncorporatedInventors: Murtaza Ali, Shahedolla Molla, Narasimhan Venkatraman, Channamallesh Hiremath, Umashankar S. Iyer, Udayan Dasgupta, Austin Paul Hunt, Dennis G. Mannering
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Patent number: 7496134Abstract: An integrated circuit 18 is provided that includes a memory 32 and a memory modification component 33. The memory 32 maintains a bits count, a gain, and a tone order for each of a plurality of discrete multi-tone sub-channels. The memory modification component 33 operable to control an in-service modification of at least some of the bits count, the gain, and the tone order using a single bits, gains and tone order table.Type: GrantFiled: January 26, 2005Date of Patent: February 24, 2009Assignee: Texas Instruments IncorporatedInventors: Arthur J. Redfern, Udayan Dasgupta
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Patent number: 7352823Abstract: Method for computing distances to received data points. A preferred embodiment comprises determining a first point on a grid nearest to the received point, computing a second point closest to the received point inside a specified area, wherein the second point is a point in a first coset, computing a third, fourth, and fifth point, wherein each point is a member of a different coset and each point is the closest point in its coset to the received point, and computing a distance from the received point to each of the second, third, fourth, and fifth points.Type: GrantFiled: December 30, 2003Date of Patent: April 1, 2008Assignee: Texas Instruments IncorporatedInventors: Udayan Dasgupta, Fernando A. Mujica, Murtaza Ali
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Patent number: 7298207Abstract: Systems and methods are disclosed for providing automatic gain control of a multi-stage system. A method can include defining at least one parameter that is adapted to at least one of maximize hardware capacity of each of a plurality of gain stages and mitigate part-to-part variations of the multi-stage system. An order is selected for training the plurality of stages based on relative noise dominance for the plurality of stage. For a given stage of the plurality of stages, which is selected according to the selected order, output signals of the multi-stage system are measured over a plurality of gain settings for the given stage. A gain setting of the given stage of the multi-stage system also is configured based on the measured output signals relative to the at least one parameter defined for the given stage. The plurality of gain stages can include an analog equalizer as well programmable gain amplifiers connected in series.Type: GrantFiled: October 15, 2004Date of Patent: November 20, 2007Assignee: Texas Instruments IncorporatedInventors: Susan Yim, Udayan Dasgupta, Sandeep Oswal, Murtaza Ali
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Patent number: 7190717Abstract: A system and method for reordering tones of a DMT signal within a communication system is described. Cross tone correlated noise in a received signal is identified and rearranged such that tones with correlated noise are spread out throughout the received signal before being processed by a decoder such as, Viterbi decoder. In an embodiment, two tones with the most correlated noise are placed at each end of the sequence of tones presented to the Viterbi decoder. In some embodiment, the tones with correlated noise can be spread such that two adjacent tones with correlated noise have a minimum distance of at least three tones between them at the input to the Viterbi decoder. In other embodiment, tones in the received signal can be processed in various kinds of interleavers for reordering according to the interleaver scheme.Type: GrantFiled: September 22, 2005Date of Patent: March 13, 2007Assignee: Texas Instruments IncorporatedInventors: Channamallesh G. Hiremath, Udayan Dasgupta, Zigang Yang, Umashanker S. Iyer, Michael E. Locke
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Publication number: 20060095581Abstract: A client premises digital subscriber line (DSL) modem having multi-mode capability is disclosed. In initialization, the modem estimates whether channel conditions are such that digital processing of the received data according to a lower data rate DSL standard, such as ADSL2, may result in a higher effective data rate than receipt and processing according to a higher data rate DSL standard, such as ADSL2+. If so, the DSL modem configures itself, such as by configuring its filter characteristics and sampling frequency, to receive and process data according to the lower data rate DSL standard; the transmitting modem, for example at a central office or service area interface, may continue to operate according to the higher data rate standard (with its bit loading corresponding to a subset of subchannels). The receiving DSL modem processes the payload data according to the lower standard, while processing control messages according to the higher standard.Type: ApplicationFiled: September 6, 2005Publication date: May 4, 2006Applicant: Texas Instruments IncorporatedInventors: Murtaza Ali, Shahedolla Molla, Narasimhan Venkatraman, Channamallesh Hiremath, Umashankar Iyer, Udayan Dasgupta, Austin Hunt, Dennis Mannering
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Patent number: 7023929Abstract: A method of providing an improved transfer function for a Discrete Multitone (DMT) type modulation transmitter with digital filtering after modulation followed by digital to analog converter and analog filtering is provided by sending a test signal to said transmitter and measuring the results of the test signal to determine the transfer function. The inverse of the transfer function that needs to be compensated is determined and the inverse of transfer function to be compensated is truncated to the region of interest (H2). The desired band split component of pre-compensation filter is designed (H3). The desired target frequency response of the pre-compensation filter is determined by H4=H2*H3 where H4 is the multiplication of H2 and H3 Given the target frequency response in H4 Hermetian symmetry is imposed on the frequency response. The inverse Fourier transform (IFFT) is taken to generate a time domain filter, h5. The characteristic of this filter is added at the digital filtering after modulation.Type: GrantFiled: July 10, 2002Date of Patent: April 4, 2006Assignee: Texas Instruments IncorporatedInventors: Fernando A. Mujica, Udayan Dasgupta, Mangesh Sadafale, Sandeep Oswal, Prakash Easwaran