Patents by Inventor Udayan Dasgupta

Udayan Dasgupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060062289
    Abstract: A system and method for reordering tones of a DMT signal within a communication system is described. Cross tone correlated noise in a received signal is identified and rearranged such that tones with correlated noise are spread out throughout the received signal before being processed by a decoder such as, Viterbi decoder. In an embodiment, two tones with the most correlated noise are placed at each end of the sequence of tones presented to the Viterbi decoder. In some embodiment, the tones with correlated noise can be spread such that two adjacent tones with correlated noise have a minimum distance of at least three tones between them at the input to the Viterbi decoder. In other embodiment, tones in the received signal can be processed in various kinds of interleavers for reordering according to the interleaver scheme.
    Type: Application
    Filed: September 22, 2005
    Publication date: March 23, 2006
    Inventors: Channamallesh Hiremath, Udayan Dasgupta, Zigang Yang, Umashanker Iyer, Michael Locke
  • Patent number: 6983032
    Abstract: The present invention provides an apparatus, system and method for synchronizing a local clock signal with a remote clock signal in a communication network. Phase information is used to calculate a number of “clock jitters” per unit of time needed to synchronize the locally generated clock with the remote clock. Introducing (removing) a given amount of delay at a particular point in the local clock signal results in a positive (negative) jitter in which its minimum value defines the jitter resolution. The jitters are introduced to the local clock signal from a plurality of tapped delay line elements (310) selected by a phase selector (350) in response to a timing correction signal issued by a phase error module (520).
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: January 3, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Fernando A. Mujica, Udayan Dasgupta, Sandeep Kesrimal Oswal, Murtaza Ali, Pradeep Kiran Sarvepalli, Prakash Easwaran, Diptendra Narayan Basu
  • Publication number: 20050169358
    Abstract: An integrated circuit 18 is provided that includes a memory 32 and a memory modification component 33. The memory 32 maintains a bits count, a gain, and a tone order for each of a plurality of discrete multi-tone sub-channels. The memory modification component 33 operable to control an in-service modification of at least some of the bits count, the gain, and the tone order using a single bits, gains and tone order table.
    Type: Application
    Filed: January 26, 2005
    Publication date: August 4, 2005
    Applicant: Texas Instruments Incorporated
    Inventors: Arthur Redfern, Udayan Dasgupta
  • Publication number: 20050127993
    Abstract: Systems and methods are disclosed for providing automatic gain control of a multi-stage system. A method can include defining at least one parameter that is adapted to at least one of maximize hardware capacity of each of a plurality of gain stages and mitigate part-to-part variations of the multi-stage system. An order is selected for training the plurality of stages based on relative noise dominance for the plurality of stage. For a given stage of the plurality of stages, which is selected according to the selected order, output signals of the multi-stage system are measured over a plurality of gain settings for the given stage. A gain setting of the given stage of the multi-stage system also is configured based on the measured output signals relative to the at least one parameter defined for the given stage. The plurality of gain stages can include an analog equalizer as well programmable gain amplifiers connected in series.
    Type: Application
    Filed: October 15, 2004
    Publication date: June 16, 2005
    Inventors: Susan Yim, Udayan Dasgupta, Sandeep Oswal, Murtaza Ali
  • Publication number: 20050026572
    Abstract: A noise determiner for use with a communications system, a method of determining noise in a communications system and a digital subscriber line (DSL) modem. In one embodiment, the noise determiner includes (1) a crosstalk identifier that detects directly a noise source in a frequency domain from observed noise associated with the communications system and (2) a crosstalk estimator coupled to the crosstalk identifier and that provides a corresponding level of the noise source.
    Type: Application
    Filed: July 28, 2003
    Publication date: February 3, 2005
    Applicant: Texas Instruments Incorporated
    Inventors: Udayan Dasgupta, Zigang Yang, Arthur Refern, Murtaza Ali
  • Publication number: 20040267852
    Abstract: Method for computing distances to received data points. A preferred embodiment comprises determining a first point on a grid nearest to the received point, computing a second point closest to the received point inside a specified area, wherein the second point is a point in a first coset, computing a third, fourth, and fifth point, wherein each point is a member of a different coset and each point is the closest point in its coset to the received point, and computing a distance from the received point to each of the second, third, fourth, and fifth points.
    Type: Application
    Filed: December 30, 2003
    Publication date: December 30, 2004
    Inventors: Udayan Dasgupta, Fernando A. Mujica, Murtaza Ali
  • Publication number: 20040114676
    Abstract: An upstream signal optimizer for use with a digital subscriber line (DSL) modem, a method of optimizing an upstream signal and a transmitter associated with a DSL modem. In one embodiment, the upstream signal optimizer includes (1) a signal adapter configured to shape a frequency domain of an upstream signal and (2) an adapter controller coupled to the signal adapter configured to control operation of the signal adapter based on a training sequence of the modem.
    Type: Application
    Filed: August 13, 2003
    Publication date: June 17, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Udayan Dasgupta, Mustafa Turkboylari, Umashankar Iyer
  • Publication number: 20040008793
    Abstract: A method of providing an improved transfer function for a Discrete Multitone (DMT) type modulation transmitter with digital filtering after modulation followed by digital to analog converter and analog filtering is provided by sending a test signal to said transmitter and measuring the results of the test signal to determine the transfer function. The inverse of the transfer function that needs to be compensated is determined and the inverse of transfer function to be compensated is truncated to the region of interest (H2). The desired band split component of pre-compensation filter is designed (H3). The desired target frequency response of the pre-compensation filter is determined by H4=H2*H3 where H4 is the multiplication of H2 and H3 Given the target frequency response in H4 Hermetian symmetry is imposed on the frequency response. The inverse Fourier transform (IFFT) is taken to generate a time domain filter, h5. The characteristic of this filter is added at the digital filtering after modulation.
    Type: Application
    Filed: July 10, 2002
    Publication date: January 15, 2004
    Inventors: Fernando A. Mujica, Udayan Dasgupta, Mangesh Sadafale, Sandeep Oswal, Prakash Easwaran
  • Publication number: 20030043945
    Abstract: The present invention provides an apparatus, system and method for synchronizing a local clock signal with a remote clock signal in a communication network. Phase information is used to calculate a number of “clock jitters” per unit of time needed to synchronize the locally generated clock with the remote clock. Introducing (removing) a given amount of delay at a particular point in the local clock signal results in a positive (negative) jitter in which its minimum value defines the jitter resolution. The jitters are introduced to the local clock signal from a plurality of tapped delay line elements (310) selected by a phase selector (350) in response to a timing correction signal issued by a phase error module (520).
    Type: Application
    Filed: August 28, 2001
    Publication date: March 6, 2003
    Inventors: Fernando A. Mujica, Udayan Dasgupta, Sandeep Kesrimal Oswal, Murtaza Ali, Pradeep Kiran Sarvepalli, Prakash Easwaran, Diptendra Narayan Basu