Abstract: A method to form copper-cobalt interconnects comprises rinsing a copper substrate with deionized water, heating a mild etchant solution and rinsing the copper substrate with the heated mild etchant solution, heating an electroless plating solution and rinsing the copper substrate with a portion of the heated electroless plating solution, heating a reducing agent solution and mixing another portion of the heated electroless plating solution with the heated reducing agent solution to form a self-catalytic bath, and applying the self-catalytic bath to the copper substrate. The electroless plating solution may contain cobalt ions. The method may further include rinsing the copper substrate with deionized water and a hydrofluoric acid solution after the application of the self-catalytic bath.

Abstract: An apparatus that includes an electroosmotic pump and an aqueous or nonaqueous electrolyte liquid and generates relatively low amount of hydrogen gas is described herein. The apparatus may further include a hydrogen absorber.

Abstract: Some embodiments for a method to fill interlayer vias with a suitable metal in a ferroelectric polymer memory die to reduce the step height and improve the thermal and electrical properties of the via. The method uses an electroless plating method to fill the vias, which is compatible with the ferroelectric polymer memory die processing temperature limits. The resulting process produces via fill metal plugs in the ferroelectric memory die, which allows for the deposition of a thin metal layer over the vias, while at the same time improving the electrical and thermal properties of the vias. Other embodiments are described and claimed herein.

Abstract: A method for making a compliant interconnect with two or more layers of metal is described herein.

Abstract: An embodiment of the invention provides a method for reducing within die thickness variations by modifying the concentration of components of a low-acid electroplating solution. For one embodiment, the leveler concentration is increased sufficiently to reduce within die thickness variations to a specified value. For one embodiment of the invention, the leveler and suppressor are increased to reduce within die thickness variations and substantially reduce a plurality of electroplating defects. In such an embodiment the combined concentration of leveler and suppressor is determined to maintain adequate gap fill.

Abstract: A multiple stage method of electrolessly depositing a metal layer is presented. This method may have the two main stages of first forming a thin metal layer on a metal surface using an electroless plating solution containing activating agents that are highly reactive reducing agents, and second, forming a bulk metal layer over the thin metal layer by using an electroless plating solution containing mildly reactive reducing agents. Through this two stage method, the use of highly reactive reducing agents that may cause the formation of contaminant particles may be minimized. By minimizing the formation of contaminant particles in the electroless plating solution, the lifetime of the solution may be extended and the current leakage between metal interconnect lines may be reduced.

Abstract: A multiple stage method of electrolessly depositing a metal layer is presented. This method may have the two main stages of first forming a thin metal layer on a metal surface using an electroless plating solution containing activating agents that are highly reactive reducing agents, and second, forming a bulk metal layer over the thin metal layer by using an electroless plating solution containing mildly reactive reducing agents. Through this two stage method, the use of highly reactive reducing agents that may cause the formation of contaminant particles may be minimized. By minimizing the formation of contaminant particles in the electroless plating solution, the lifetime of the solution may be extended and the current leakage between metal interconnect lines may be reduced.

Abstract: A method of forming a copper interconnect, comprising forming an opening in a dielectric layer disposed on a substrate, forming a barrier layer over the opening, forming a seed layer over the metal layer, and forming a copper-noble metal alloy layer by electroplating and/or electroless deposition on the seed layer. The copper-noble metal alloy improves the electrical characteristics and reliability of the copper interconnect.

Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.

Abstract: A method of fabricating an integrated circuit comprises forming or providing a solution containing carbon nanotubes and forming a metal layer utilizing the solution.

Abstract: An apparatus includes a condensed array addressed device; and a spectroscope optically coupled to the condensed array addressed device. A method includes determining bonding and/or lack-of-bonding of a target molecule to a condensed array addressed device by characterizing a subsequent rate of electrolysis on the condensed array addressed device. A method includes fabricating a condensed array addressed device using damascene patterning.

Abstract: The invention provides bumps between a die and a substrate with a height greater than or equal to a height of a waveguide between the die and the substrate. The bumps may be formed on a die prior to that die being singulated from a wafer.

Abstract: The inventor devised methods of forming interconnects that result in conductive structures with fewer voids and thus reduced electrical resistance. One embodiment of the method starts with an insulative layer having holes and trenches, fills the holes using a selective electroless deposition, and fills the trenches using a blanket deposition. Another embodiment of this method adds an anti-bonding material, such as a surfactant, to the metal before the electroless deposition, and removes at least some the surfactant after the deposition to form a gap between the deposited metal and interior sidewalls of the holes and trenches. The gap serves as a diffusion barrier. Another embodiments leaves the surfactant in place to serve as a diffusion barrier. These and other embodiments ultimately facilitate the speed, efficiency, or fabrication of integrated circuits.

Abstract: Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

Abstract: Electroless plating systems and methods are described herein.

Abstract: A method and apparatus for a semiconductor device having a semiconductor device having increased conductive material reliability is described. That method and apparatus comprises forming a conductive path on a substrate. The conductive path made of a first material. A second material is then deposited on the conductive path. Once the second material is deposited on the conductive path, the diffusion of the second material into the conductive path is facilitated. The second material has a predetermined solubility to substantially diffuse to grain boundaries within the first material.

Abstract: A method for making a semiconductor device is provided including providing a substrate, and forming a dielectric layer over the substrate. The method also includes defining a damascene interconnect structure in the dielectric layer and forming a barrier layer over the dielectric layer and within the damascene interconnect structure where the barrier layer is tapered within the damascene interconnect structure.

Abstract: A metal alloy capping layer containing a group VIII metal and silicon, carbon, or nitrogen may be used to protect copper interconnects of integrated circuits from oxidation and to prevent the electromigration of copper interconnects while at the same time not effecting the performance of integrated circuit. Methods of incorporating the silicon, carbon, or nitrogen into the group VIII metal to form the metal alloy capping layer are also presented along with methods of electrolessly forming the cap on a metal interconnect line.

Abstract: A damascene process using a doped and undoped oxide ILD is described. The selectivity between the carbon doped and carbon free oxide provides an etching stop between the ILD's in addition to providing mechanical strength to the structure.

Abstract: An apparatus and method for forming catalyst particles to grow nanotubes is disclosed. In addition, an apparatus and method for forming nanotubes using the catalytic particles is also disclosed. The particles formed may have different diameters depending upon how they are formed. Once formed, the particles are deposited on a substrate. Once deposited, the mobility of the particles is restricted and nanotubes and/or nanotube portions are grown on the particles. Nanotube portions having different diameters may be formed and the portions may be connected to form nanotubes with different diameters along the length of the nanotube.