Abstract: The inventor devised methods of forming interconnects that result in conductive structures with fewer voids and thus reduced electrical resistance. One embodiment of the method starts with an insulative layer having holes and trenches, fills the holes using a selective electroless deposition, and fills the trenches using a blanket deposition. Another embodiment of this method adds an anti-bonding material, such as a surfactant, to the metal before the electroless deposition, and removes at least some the surfactant after the deposition to form a gap between the deposited metal and interior sidewalls of the holes and trenches. The gap serves as a diffusion barrier. Another embodiments leaves the surfactant in place to serve as a diffusion barrier. These and other embodiments ultimately facilitate the speed, efficiency, or fabrication of integrated circuits.

Abstract: A method for fabricating copper-aluminum metallization utilizing the technique of electroless copper deposition is described. The method provides a self-encapsulated copper-aluminum metallization structure.

Abstract: Copper or copper alloy interconnection patterns are formed by a damascene technique. An aluminum or magnesium alloy is deposited in a damascene opening formed in a dielectric layer. Copper or a copper alloy is then electroplated or electroless plated on the aluminum or magnesium alloy, filling the opening. During low temperature annealing, aluminum or magnesium atoms diffuse through the copper or copper alloy layer and accumulate on its surface forming a self-encapsulated oxide to prevent corrosion and diffusion of copper atoms.

Abstract: Gas shielding is employed to prevent metal plating on contacts during electroplating to reduce particulate contamination and increase thickness uniformity. In another embodiment, gas shielding is employed to prevent deposition on the backside and edges of a semiconductor wafer during plating.

Abstract: A method and apparatus for fabricating electrochemical copper interconnections between the component parts of an integrated circuit on a semiconductor device. A cathodic platter is provided that includes contact pins that contact the surface of a semiconductor wafer at predetermined locations during the electrochemical deposition process. The contact pins are arranged on the cathodic platter so that when placed on the surface of the semiconductor wafer the contact pins surround the perimetrical edges of each respective semiconductor device on the semiconductor wafer. Once the semiconductor wafer is properly positioned on the cathodic platter, a copper conductive layer can be electrochemically and uniformly deposited on the surface of the semiconductor device.

Abstract: Electroless plating of very thin metal films, such as copper, is accomplished with a spray processor. Atomized droplets or a continuous stream of an electroless plating solution are sprayed on a substrate. The electroless plating solution may be prepared by mixing a reducing solution and a metal stock solution immediately prior to the spraying. The deposition process may be carried out in an apparatus which includes metal stock solution and reducing reservoirs, a mixing chamber for forming the plating solution, optionally an inert gas or air (oxygen) source, a process chamber in which the solution is sprayed on the substrate and a control system for providing solutions to the mixing chamber and the process chamber in accordance with a predetermined program for automated mixing and spraying of the plating solution. The process can be used to form metal films as thin as 100 .ANG.

Abstract: High aspect ratio openings in excess of 3, such as trenches, via holes or contact holes, in a dielectric layer are voidlessly filled employing a pulse or forward-reverse pulse electroplating technique to deposit copper or a copper-base alloy. A leveling agent is incorporated in the electroplating composition to ensure that the opening is filled substantially sequentially from the bottom upwardly.

Abstract: A high conductivity interconnect structure is formed by electroplating or electroless plating of Cu or a Cu-base alloy on a seed layer comprising an alloy of a catalytically active metal, such as Cu, and a refractory metal, such as Ta. The seed layer also functions as a barrier/adhesion layer for the subsequently plated Cu or Cu-base alloy. Another embodiment comprises initially depositing a refractory metal barrier layer before depositing the seed layer.

Abstract: Copper or a copper alloy is electroplated to fill via/contact holes and/or trenches in a dielectric layer. A barrier layer is initially deposited on the dielectric layer lining the hole/trench. A thin conformal layer of copper or a copper alloy is sputter deposited on the barrier layer outside the hole/trench. Copper or a copper alloy is then electroplated on the conformal copper or copper alloy layer and filling the hole/trench. During electroplating, the barrier layer functions as a seed layer within the hole/trench while the sputter deposited conformal copper or copper alloy layer enhances the flow of electrons from the wafer edge inwardly to provide a favorable deposition rate.

Abstract: A method for fabricating copper-aluminum metallization utilizing the technique of electroless copper deposition is described. The method provides a self-encapsulated copper-aluminum metallization structure.

Abstract: Gas shielding is employed to prevent metal plating on contacts during electroplating to reduce particulate contamination and increase thickness uniformity. In another embodiment, gas shielding is employed to prevent deposition on the backside and edges of a semiconductor wafer during plating.

Abstract: A method for electroplating a silicon substrate in manufacturing a semiconductive device is provided. Electroplating process chamber contacts or fingers used in positioning a silicon substrate or wafer during an electroplating process are plated with a metal layer to prevent oxidation of the contacts. Oxidation of the contacts may result in increased and varying resistance of the contacts and thus nonuniform plating of the silicon wafer and possibly even deplating of a seed layer. A 20 mA/cm.sup.2 current is applied to the contacts which are immersed in an electrolyte solution before loading a silicon wafer. A silicon wafer is then loaded into the electroplating process chamber containing the electrolyte solution. The preplating of the contacts enables the formation of a uniform metal layer on the silicon substrate. Additionally, voltage then may be applied to the contacts after unloading the silicon wafer to reduce oxidation.

Abstract: Gas shielding is employed to prevent metal plating on contacts during electroplating to reduce particulate contamination and increase thickness uniformity. In another embodiment, gas shielding is employed to prevent deposition on the backside and edges of a semiconductor wafer during plating.