Patents by Inventor Veronique Sousa
Veronique Sousa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9082965Abstract: A memory device including: one inert electrode including an electrically conductive material, a part of at least one material of resistivity higher than that of the material of the inert electrode, positioned around the inert electrode, a solid electrolyte positioned on at least one part of the inert electrode and of the part of electrically insulating material, and including metal ions originating from an ionizable metal part positioned on the solid electrolyte. The ratio between the coefficient of electrical resistivity of the material of resistivity higher than that of the material of the inert electrode and the coefficient of electrical resistivity of the material of the inert electrode is equal to or higher than approximately 100, and the coefficient of thermal conductivity of the electrically insulating material is equal to or higher than approximately 10 W·m?1·K?1.Type: GrantFiled: July 27, 2009Date of Patent: July 14, 2015Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Cyril Dressler, Veronique Sousa
-
Patent number: 9018614Abstract: A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a central region laterally surrounded with a peripheral region, the crystallization and melting temperatures of the central region being respectively lower than those of the peripheral region.Type: GrantFiled: September 4, 2013Date of Patent: April 28, 2015Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Jean-Francois Nodin, Veronique Sousa, Sandrine Lhostis
-
Patent number: 8759808Abstract: A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a first region adjacent to a second region itself adjacent to at least one third region, the first, second, and third regions each extending from the upper electrode to the lower electrode, the crystallization temperature of the second region ranging between that of the first region and that of the third region, and the melting temperatures of the first, second, and third regions being substantially identical.Type: GrantFiled: September 4, 2013Date of Patent: June 24, 2014Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Jean-Francois Nodin, Veronique Sousa, Sandrine Lhostis
-
Publication number: 20140070158Abstract: A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a central region laterally surrounded with a peripheral region, the crystallization and melting temperatures of the central region being respectively lower than those of the peripheral region.Type: ApplicationFiled: September 4, 2013Publication date: March 13, 2014Applicants: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SASInventors: Jean-Francois Nodin, Veronique Sousa, Sandrine Lhostis
-
Publication number: 20140070163Abstract: A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a first region adjacent to a second region itself adjacent to at least one third region, the first, second, and third regions each extending from the upper electrode to the lower electrode, the crystallization temperature of the second region ranging between that of the first region and that of the third region, and the melting temperatures of the first, second, and third regions being substantially identical.Type: ApplicationFiled: September 4, 2013Publication date: March 13, 2014Applicants: Commissariat à I'Énergie Atomique et aux Énergies Alternatives, STMicroelectronics (Crolles 2) SASInventors: Jean-Francois Nodin, Veronique Sousa, Sandrine Lhostis
-
Publication number: 20120307552Abstract: A process of producing a resistivity-change memory cell is described. The process includes a deposition at room temperature, in amorphous state, of a layer of a nitrogen (N)-doped alloy of germanium (Ge) and tellurium (Te) to constitute the resistivity-change material of the memory cell. An annealing is then performed such as to limit the type of re-crystallisation by nucleation starting from the amorphous state of the phase-change material. The material used and the process permit the data retention at high temperature to be significantly improved.Type: ApplicationFiled: June 3, 2011Publication date: December 6, 2012Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE. ALT.Inventors: Luca PERNIOLA, Veronique SOUSA
-
Patent number: 8232542Abstract: A phase-change memory cell including, between two electrical contacts, a portion in a memory material with amorphous-crystalline phase-change and vice versa, as a stack with a central area located between two outmost areas. An interface, inert or quasi-inert from a physico-chemical point of view, is present between the active central area and each passive outmost area. Each passive outmost area is made in a material having a melting temperature higher than that of the material of the active central area.Type: GrantFiled: November 2, 2004Date of Patent: July 31, 2012Assignee: Commissariat a l'Energie AtomiqueInventors: Véronique Sousa, Pierre Desre
-
Patent number: 8148709Abstract: This magnetic device integrates a magneto-resistive stack, the stack comprising at least two layers made out of a ferromagnetic material, separated from each other by a layer of non-magnetic material; and means for causing an electron current to flow perpendicular to the plane of the layers, with at least one integrated nano-contact intended to inject the current into the magneto-resistive stack. The nano-contact is made in a bilayer composed of a solid electrolyte on which has been deposited a soluble electrode composed of a metal that has been at least partially dissolved in the electrolyte.Type: GrantFiled: February 5, 2009Date of Patent: April 3, 2012Assignee: Commissariat a l'Energie AtomiqueInventors: Bertrand Delaet, Marie-Claire Cyrille, Jean-François Nodin, Véronique Sousa
-
Patent number: 8098105Abstract: This radio-frequency oscillator includes a magnetoresistive device in which an electric current is able to flow. The magnetoresistive device includes a first magnetic layer, known as a “trapped layer”, whereof the magnetization is of fixed direction. The magnetoresistive device further includes a second magnetic layer known as a “free layer” and a non-magnetic layer, known as an “intermediate layer”, interposed between the first and second layer, known as the intermediate layer. The oscillator further includes means capable of causing an electron current to flow in said layers constituting the aforementioned stack and in a direction perpendicular to the plane which contains said layers. One of the three layers constituting the magnetoresistive device includes at least one constriction zone of the electric current passing through it.Type: GrantFiled: November 18, 2009Date of Patent: January 17, 2012Assignee: Commissariat à I'Energie AtomiqueInventors: Marie-Claire Cyrille, Bertrand Delaet, Jean-Francois Nodin, Veronique Sousa
-
Patent number: 8048713Abstract: The invention relates to a process for manufacturing a plurality of CBRAM memories, each comprising a memory cell in a chalcogenide solid electrolyte, an anode, and a cathode, the process comprising implementing a sublayer of a high thermal conductivity material, higher than 1.3 W/m/K, which covers the set of contacts, then providing, on said sublayer, a triple layer comprising a chalcogenide layer, then an anodic layer, and a layer with second contacts (36), and finally an etching step.Type: GrantFiled: October 13, 2008Date of Patent: November 1, 2011Assignee: Commissariat a l'Energie AtomiqueInventors: Véronique Sousa, Cyril Dressler
-
Patent number: 8021953Abstract: A microelectronic device includes: at least one cell or element including at least one first electrode, at least one second electrode, and at least one stack of thin layers between the first electrode and the second electrode. The stack includes at least one doped chalcogenide layer capable of forming a solid electrolyte, the doped chalcogenide layer being provided on and in contact with the first electrode; at least one interface layer provided on and in contact with the doped chalcogenide layer, the interface layer being based on a material different from the chalcogenide, the material being carbon or carbon comprising a metallic additive or a semiconducting additive; and at least one metallic ion donor layer provided on and in contact with the interface layer, the metallic ion donor layer being an ion source for the solid electrolyte.Type: GrantFiled: May 28, 2010Date of Patent: September 20, 2011Assignee: Commissariat a l'Energie AtomiqueInventors: Cyril Dressler, Veronique Sousa
-
Publication number: 20110121254Abstract: A memory device including: one inert electrode including an electrically conductive material, a part of at least one material of resistivity higher than that of the material of the inert electrode, positioned around the inert electrode, a solid electrolyte positioned on at least one part of the inert electrode and of the part of electrically insulating material, and including metal ions originating from an ionizable metal part positioned on the solid electrolyte. The ratio between the coefficient of electrical resistivity of the material of resistivity higher than that of the material of the inert electrode and the coefficient of electrical resistivity of the material of the inert electrode is equal to or higher than approximately 100, and the coefficient of thermal conductivity of the electrically insulating material is equal to or higher than approximately 10 W·m?1·K?1.Type: ApplicationFiled: July 27, 2009Publication date: May 26, 2011Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALTInventors: Cyril Dressler, Veronique Sousa
-
Patent number: 7876605Abstract: A phase change memory having a memory material layer consisting of a phase change material, and a first and second electrical contact which are located at a distance from one another and via which a switching zone of the memory material layer can be traversed by a current signal, wherein the current signal can be used to induce a reversible phase change between a crystalline phase and an amorphous phase and thus a change in resistance of the phase change material in the switching zone. The invention also relates to a phase change memory assembly, a phase change memory cell, a 2D phase change memory cell array, a 3D phase change memory cell array and an electronic component.Type: GrantFiled: October 19, 2004Date of Patent: January 25, 2011Assignees: Rheinisch-Westfaelische Technische Hochschle Aachen, Commisssariat a l'Energie AtomiqueInventors: Peter Haring Bolivar, Bernard Bechevet, Veronique Sousa, Dae-Hwang Kim, Heinrich Kurz, Florian Merget
-
Publication number: 20100291748Abstract: A microelectronic device includes: at least one cell or element including at least one first electrode, at least one second electrode, and at least one stack of thin layers between the first electrode and the second electrode. The stack includes at least one doped chalcogenide layer capable of forming a solid electrolyte, the doped chalcogenide layer being provided on and in contact with the first electrode; at least one interface layer provided on and in contact with the doped chalcogenide layer, the interface layer being based on a material different from the chalcogenide, the material being carbon or carbon comprising a metallic additive or a semiconducting additive; and at least one metallic ion donor layer provided on and in contact with the interface layer, the metallic ion donor layer being an ion source for the solid electrolyte.Type: ApplicationFiled: May 28, 2010Publication date: November 18, 2010Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUEInventors: Cyril DRESSLER, Véronique SOUSA
-
Patent number: 7833822Abstract: A microelectronic device includes: at least one cell or element including at least one first electrode, at least one second electrode, and at least one stack of thin layers between the first electrode and the second electrode. The stack includes at least one doped chalcogenide layer capable of forming a solid electrolyte, the doped chalcogenide layer being provided on and in contact with the first electrode; at least one interface layer provided on and in contact with the doped chalcogenide layer, the interface layer being based on a material different from the chalcogenide, the material being carbon or carbon comprising a metallic additive or a semiconducting additive; and at least one metallic ion donor layer provided on and in contact with the interface layer, the metallic ion donor layer being an ion source for the solid electrolyte.Type: GrantFiled: December 21, 2006Date of Patent: November 16, 2010Assignee: Commissariat A l'Energie AtomiqueInventors: Cyril Dressler, Véronique Sousa
-
Patent number: 7804704Abstract: A PMC memory including: a memory cell, the memory cell including, an active zone, a heating element disposed outside of the active zone, and at least two contacts that apply a writing voltage to the memory cell, wherein the heating element transitionally heats the memory cell-during a writing process in the memory cell to a writing temperature higher than an operating temperature of the memory cell outside the writing process.Type: GrantFiled: December 20, 2005Date of Patent: September 28, 2010Assignee: Commissariat A l'Energie AtomiqueInventor: Veronique Sousa
-
Publication number: 20100134196Abstract: This radio-frequency oscillator includes a magnetoresistive device in which an electric current is able to flow. The magnetoresistive device includes a first magnetic layer, known as a “trapped layer”, whereof the magnetization is of fixed direction. The magnetoresistive device further includes a second magnetic layer known as a “free layer” and a non-magnetic layer, known as an “intermediate layer”, interposed between the first and second layer, known as the intermediate layer. The oscillator further includes means capable of causing an electron current to flow in said layers constituting the aforementioned stack and in a direction perpendicular to the plane which contains said layers. One of the three layers constituting the magnetoresistive device includes at least one constriction zone of the electric current passing through it.Type: ApplicationFiled: November 18, 2009Publication date: June 3, 2010Applicant: Commissariat A L'Energie AtomiqueInventors: Marie-Claire Cyrille, Bertrand Delaet, Jean-Francois Nodin, Veronique Sousa
-
Publication number: 20090250775Abstract: This magnetic device integrates a magneto-resistive stack, the stack comprising at least two layers made out of a ferromagnetic material, separated from each other by a layer of non-magnetic material; and means for causing an electron current to flow perpendicular to the plane of the layers, with at least one integrated nano-contact intended to inject the current into the magneto-resistive stack. The nano-contact is made in a bilayer composed of a solid electrolyte on which has been deposited a soluble electrode composed of a metal, and at least partially dissolved in the electrolyte.Type: ApplicationFiled: February 5, 2009Publication date: October 8, 2009Applicant: Commissariat A L'Energie AtomiqueInventors: Bertrand Delaet, Marie-Claire Cyrille, Jean-Francois Nodin, Veronique Sousa
-
Publication number: 20090098681Abstract: The invention relates to a process for manufacturing a plurality of CBRAM memories, each comprising a memory cell in a chalcogenide solid electrolyte, an anode, and a cathode, the process comprising implementing a sublayer of a high thermal conductivity material, higher than 1.3 W/m/K, which covers the set of contacts, then providing, on said sublayer, a triple layer comprising a chalcogenide layer, then an anodic layer, and a layer with second contacts (36), and finally an etching step.Type: ApplicationFiled: October 13, 2008Publication date: April 16, 2009Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUEInventors: Veronique Sousa, Cyril Dressler
-
Publication number: 20080101109Abstract: A phase change memory having a memory material layer consisting of a phase change material, and a first and second electrical contact which are located at a distance from one another and via which a switching zone of the memory material layer can be traversed by a current signal, wherein the current signal can be used to induce a reversible phase change between a crystalline phase and an amorphous phase and thus a change in resistance of the phase change material in the switching zone. The invention also relates to a phase change memory assembly, a phase change memory cell, a 2D phase change memory cell array, a 3D phase change memory cell array and an electronic component.Type: ApplicationFiled: October 19, 2004Publication date: May 1, 2008Inventors: Peter Haring-Bolivar, Bernard Bechevet, Veronique Sousa, Dae-Hwang Kim, Heinrich Kurz, Florian Merget