Abstract: A method and apparatus for managing task context is provided. Upon initialization, a protocol engine provides context resources available for processing tasks to a task issuer. Based on available context resources, the task issuer creates and manages a free list of available task context indices and assigns an index to a task prior to storing task context in a context memory accessible to both the task issuer and the protocol engine and issuing the task to the protocol engine.

Abstract: According to one embodiment, a system is disclosed. The system includes one or more storage devices, a host bus adapter (HBA) and a bridging device coupled between the one or more storage device and the HBA. The bridging device includes a register having bits corresponding to each of the one or more storage devices. Each bit indicates whether staggered spin-up is enabled at a corresponding storage device.

Abstract: According to one embodiment, a host device is disclosed. The host device includes a logic component to provide an indication of a number of commands issued to a target device, and a task scheduler to schedule commands based on the number of issued commands provided by the logic component.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.

Abstract: According to one embodiment, a system is disclosed. The system includes an initiator device to transmit input/output (I/O) write data and a target device, coupled to the initiator device, to receive the write data from the initiator device as a first segment of data and a second segment of data. The target device re-transmits a transfer ready frame to force the initiator device to retransmit the second segment in response to detecting an uncorrectable error in the second segment.

Abstract: According to one embodiment, a system is disclosed. The system includes a central timeout manager (CTM) to receive timeout events from two or more clients and a search unit to search for a location in a list of timeout events to place a new received timeout event.

Abstract: According to one embodiment, a storage device is disclosed. The storage device includes a port having one or more lanes and a direct memory access (DMA) Descriptor Manager (DM). The DM generates and tracks completion of descriptors. The DM includes a first completion lookup table to track one or more fields of an input/output (I/O) context received at a first lane.

Abstract: A multi-function peripheral component interconnect (PCI) device is disclosed. The device includes a first configuration data structure associated with a first PCI function, a second configuration data structure associated with a second PCI function and a PCI bridge, coupled the first and second configuration data structures. The PCI bridge processes transactions on behalf of the first and second functions.

Abstract: A storage device is disclosed. The storage device includes a storage controller. The storage controller includes a direct memory access (DMA) Descriptor Manager (DM) to generate DMA descriptors by monitoring user data and a data integrity field (DIF) transferred between a host memory and a local memory based upon a function being performed.

Abstract: A frame based data transfer device includes a receive frame parser, a receive frame processor, and a DMA engine. The receive frame parser receives a frame, stores framing information from the frame in a receive header queue, and stores an information unit from the frame in an information unit buffer. The receive frame processor is coupled to the receive header queue. The receive frame processor reads a transport layer task context as determined by a tag field in the framing information, determines how to handle the frame from the transport layer task context and framing information, generates a DMA descriptor, and stores an updated transport layer task context. The DMA engine is coupled to the information unit buffer and receive frame processor. The DMA engine reads a DMA task context, transfers the information unit to a destination memory by processing the DMA descriptor, and stores an updated DMA task context.

Abstract: According to one embodiment, a system is disclosed. The system includes one or more storage devices, a host bus adapter (HBA) and a bridging device coupled between the one or more storage device and the HBA. The bridging device includes a register having bits corresponding to each of the one or more storage devices. Each bit indicates whether staggered spin-up is enabled at a corresponding storage device.

Abstract: An embodiment of the present invention is a technique to process a plurality of I/O sequences associated with a storage device. A task context pre-fetch engine pre-fetches a task context from a task context memory based on a pre-fetch request. At least a multi-threaded transmit transport layer (T×TL) processes the plurality of I/O sequences from an I/O pool simultaneously. The multi-threaded T×TL generates the pre-fetch request and one or more frames from the plurality of I/O sequences. A switch fabric and controller routes the frame to a link layer associated with the storage device.

Abstract: A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.

Abstract: Disclosed is an initiator port that implements a transport layer retry (TLR) mechanism. The initiator port includes a circuit having a transmit transport layer and receive transport layer in which both the transmit and receive transport layers are coupled to a link. A transmit protocol processor of the transmit transport layer controls a TLR mechanism in a serialized protocol. A receive protocol processor of the receive transport layer is coupled to the transmit transport layer and likewise controls the TLR mechanism in the serialized protocol.

Abstract: Methods and apparatus for target-side SATA NCQ tag management are disclosed. In one aspect, an apparatus may include a status memory and a status manager circuit in communication with the status memory. The status memory may store status information for each of a plurality of commands that have been queued according to Native Command Queuing (NCQ). The status information may indicate whether or not each of the commands has been completed. The status manager circuit may generate and provide a status signal based on the status information stored in the status memory. Systems including such an apparatus and other components, such as hard disks, are also disclosed.

Abstract: Apparatus and systems, as well as methods and articles, may bridge between a link layer and a transport layer in a multi-lane serial-attached small computer system interface (SCSI)-serial SCSI protocol (SAS-SSP) device. A lane number first-in first-out buffer (FIFO) array may operate to order frame processing such that frames associated with an input-output (IO) stream subset of a plurality of SAS-SSP frames received at a plurality of lane receive buffers are processed in an IO stream subset order.

Abstract: Methods of scheduling tasks in computer systems architectures are disclosed. In one aspect, a method may include comparing a connection address of a first node with a connection address of a second node, determining that the connection address of the first node matches the connection address of the second node, and scheduling tasks to the first and second nodes based, at least in part, on the determination. Apparatus to implement task scheduling, and systems including the apparatus are also disclosed.

Abstract: Apparatus, systems, methods, and articles may operate to restrict an order of processing of frames associated with a task context stored in at least one context cache memory location. The order of processing may be restricted by selectively locking the context for exclusive use by a selected lane in a multi-lane serial-attached small computer system interface (SAS) hardware protocol engine while the selected lane processes a selected one of the frames.

Abstract: A device includes a cache memory having a locked segment and an unlocked segment. A controller is connected to the cache memory. A method partitions a cache memory into context segments and associates a context entry with at least one of the context segments if a transport layer completes processing a frame for the context entry. The at least one segment is an unlocked context segment.

Abstract: According to one embodiment of the invention, a method comprises measuring memory access latency for a prefetch cycle associated with a transmission of data from a memory device to a destination device such as a storage device. Hereafter, the prefetch rate is dynamically adjusted based on the measured memory access latency.