Abstract: A mechanism by which rule attributes of varying types and numbers can be stored and searched in an efficient manner is provided by storing attribute values of each rule in a child table of a parent rule table. The child table is normalized and contains a foreign key pointing back to the parent rule table and has attribute-value pairs as table columns of the child table. Each rule is then represented by one row of the parent rule table and one or more corresponding rows of the child rule details table. A variable and unlimited number of attribute dimensions is supported among the rules, and search performance is improved through the use of database indexes on the rule details table attribute columns. Metadata representing the structure of the child rule details table will identify the data attributes for each dimension.

Abstract: An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned in the space. Structures for detecting open circuits and short circuits are described.

Abstract: An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned in the space. Structures for detecting open circuits and short circuits are described.

Abstract: A method for making novel elevated bond-pad structures with sidewall spacers is achieved. The elevated bond-pad structures increase the space between the chip and a substrate during flip-chip bonding. The increased spacing results in better under-filling and reduces alpha particle soft errors in the chip. The sidewall spacers restrict the wetting surface for the PbSn solder bumps to the top surface of the bond pads. This results in smaller solder bumps and allows for closer spacings of the array of bonding pads for higher density integrated circuits.

Abstract: A polish apparatus for planarizing wafers and films over wafers comprising the following. A substrate chuck for holding a substrate with a surface to be polished thereof being directed about vertically. A first drive means for rotating the substrate chuck. A polishing head having a polishing surface which is adjacent to the substrate during the polishing of the substrate. The polishing surface of the polishing head is smaller than the surface of the substrate. A polishing solution supply means for supplying a polishing solution through the polishing head to the substrate held by the substrate chuck. A reciprocating means for reciprocally moving the polishing head on the surface to be polished. A pressing means for pressing the polishing pad against a substrate held by the substrate chuck by way of the polishing head. The polish head is preferably comprised of one piece of molded polymer. No polish pad is used.

Abstract: An apparatus, system, and method are disclosed for efficient recovery of a database from a log of database activities. A log of database activities is filtered into a first sequential data set. The remainder portion of the log is sorted into a second sequential data set. The first sequential data set and the second sequential data set are merged and written to the database. Allowing the sequential records to bypass a sort operation reduces the amount of time and the system resource overhead required for database recovery.

Abstract: A linear polishing apparatus for polishing a semiconductor substrate including a novel polishing belt arrangement with at least two polishing belts forming a continuous loop. Each belt having an outside polishing surface and an inside smooth surface. The belts are spaced alongside each other sharing a common axis at each end. The belts are looped around a pair of rollers making up a driver roller at one end and a driven roller at the other end. A platen member interposes each belt and is placed between the pairs of rollers. The platen provides a polishing plane and supporting surface for the polishing belts. The polishing plane includes a plurality of holes communicating with an elongated plenum chamber underlying the plane. The chamber supplies a compressed gas to impart an upward pressure against the polishing belts. The driver rollers are coupled to separate motors to independently drive and control at least said two of the polishing belts.

Abstract: A method of manufacturing a shallow trench isolation using a polishing step with reduced dishing. A pad layer, a polish stop layer, a buffer layer and a hard mask layer are formed over a substrate. The hard mask layer has a hard mask opening. We etch a trench opening in the buffer layer, the polish stop layer, the pad layer and form a trench in the substrate using the hard mask layer as an etch mask. We form an oxide trench liner layer along the sidewalls of the trench and an oxide buffer liner layer on the sidewalls of the buffer layer using a thermal oxidation. The hard mask layer prevents the oxidation of the top surface of the buffer layer during the oxidation of the oxide trench liner. This prevents the buffer layer from being consumed by the oxidation and leaves the buffer layer to act in the subsequent chemical-mechanical polish (CMP) step. Next, an insulating layer is formed at least partially filling the trench.

Abstract: A method and apparatus for shallow trench isolation. First, a layer of silicon nitride (SiN) is deposited over a semiconductor substrate. A layer of polysilicon is then deposited over the silicon nitride layer. A layer of tetraethylorthosilicate (TEOS) is deposited over the polysilicon layer. Mask and etch steps are performed to form an opening that extends through the TEOS layer and through the polysilicon layer. An etch step is then performed to etch the exposed side surfaces of the polysilicon layer. Thereby, the exposed side surfaces of the polysilicon layer are moved laterally. An etch step is then performed so as to form a trench that extends into the semiconductor substrate. Dielectric material is deposited such that the dielectric material fills the trench and fills the opening that extends through the polysilicon layer and the silicon nitride layer. The substrate is then polished using a chemical mechanical polishing process.

Abstract: A polish apparatus for planarizing wafers and films over wafers comprising the following. A substrate chuck for holding a substrate with a surface to be polished thereof being directed about vertically. A first drive means for rotating the substrate chuck. A polishing head having a polishing surface which is adjacent to the substrate during the polishing of the substrate. The polishing surface of the polishing head is smaller than the surface of the substrate. A polishing solution supply means for supplying a polishing solution through the polishing head to the substrate held by the substrate chuck. A reciprocating means for reciprocally moving the polishing head on the surface to be polished. A pressing means for pressing the polishing pad against a substrate held by the substrate chuck by way of the polishing head. The polish head is preferably comprised of one piece of molded polymer. No polish pad is used.

Abstract: A method of manufacturing a shallow trench isolation using a polishing step with reduced dishing. A pad layer, a polish stop layer, a buffer layer and a hard mask layer are formed over a substrate. The hard mask layer has a hard mask opening. We etch a trench opening in the buffer layer, the polish stop layer, the pad layer and form a trench in the substrate using the hard mask layer as an etch mask. We form an oxide trench liner layer along the sidewalls of the trench and an oxide buffer liner layer on the sidewalls of the buffer layer using a thermal oxidation. The hard mask layer prevents the oxidation of the top surface of the buffer layer during the oxidation of the oxide trench liner. This prevents the buffer layer from being consumed by the oxidation and leaves the buffer layer to act in the subsequent chemical-mechanical polish (CMP) step. Next, an insulating layer is formed at least partially filling the trench.

Abstract: A method of manufacturing a metallization scheme with an air gap formed by vaporizing a filler polymer material. The filler material is covered by a critical permeable dielectric layer. The method begins by forming spaced conductive lines over a semiconductor structure. The spaced conductive lines have top surfaces. A filler material is formed over the spaced conductive lines and the semiconductor structure. The filler material is preferably comprised of a material selected from the group consisting of polypropylene glycol (PPG), polybutadine (PB) polyethylene glycol (PEG), fluorinated amorphous carbon and polycaprolactone diol (PCL) and is formed by a spin on process or a CVD process. We etch back the filler material to expose the top surfaces of the spaced conductive lines. Next, the semiconductor structure is loaded into a HDPCVD chamber. In a critical step, a permeable dielectric layer is formed over the filler material.