Abstract: The disclosure provides example devices and methods for making and using the devices for rapid testing for the SARS-CoV-2 virus. The example device includes (a) a substrate coupled to a metal oxide layer, (b) a graphene layer coupled to the metal oxide layer, (c) a chemical or biochemical linker functionalized with the graphene layer, and (d) a plurality of SARS-CoV-2 receptors that are bound to the graphene layer via the chemical or biochemical linker, wherein the plurality of SARS-CoV-2 receptors comprise SARS-CoV-2 spike antibodies or SARS-CoV-2 spike proteins, where the graphene layer is configured to have a first phononic energy, when the plurality of SARS-CoV-2 receptors are unattached to target molecules, and a second phononic energy, when the plurality of SARS-CoV-2 receptors are attached to target molecules.

Abstract: A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN)XHy-radical interfacing with active sites on silicon nitride coated silicon (Si3N4/Si) surfaces for nucleation and growth of large-area, uniform and ultrathin h-BN directly on Si3N4/Si substrates (B/N atomic ratio=1:1.11±0.09). Further, monolayer graphene van der Waals bonded with the produced h-BN surface benefits from h-BN's reduced roughness (3.4 times) in comparison to Si3N4/Si. Because the reduced surface roughness leads to reduction in surface roughness scattering and charge impurity scattering, therefore an enhanced intrinsic charge carrier mobility (3 folds) for graphene on h-BN/Si3N4/Si is found.

Abstract: A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN)XHy-radical interfacing with active sites on silicon nitride coated silicon (Si3N4/Si) surfaces for nucleation and growth of large-area, uniform and ultrathin h-BN directly on Si3N4/Si substrates (B/N atomic ratio=1:1.11±0.09). Further, monolayer graphene van der Waals bonded with the produced h-BN surface benefits from h-BN's reduced roughness (3.4 times) in comparison to Si3N4/Si. Because the reduced surface roughness leads to reduction in surface roughness scattering and charge impurity scattering, therefore an enhanced intrinsic charge carrier mobility (3 folds) for graphene on h-BN/Si3N4/Si is found.

Abstract: A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN)XHy-radical interfacing with active sites on silicon nitride coated silicon (Si3N4/Si) surfaces for nucleation and growth of large-area, uniform and ultrathin h-BN directly on Si3N4/Si substrates (B/N atomic ratio=1:1.11±0.09). Further, monolayer graphene van der Waals bonded with the produced h-BN surface benefits from h-BN's reduced roughness (3.4 times) in comparison to Si3N4/Si. Because the reduced surface roughness leads to reduction in surface roughness scattering and charge impurity scattering, therefore an enhanced intrinsic charge carrier mobility (3 folds) for graphene on h-BN/Si3N4/Si is found.

Abstract: A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN)xHy-radical interfacing with active sites on silicon nitride coated silicon (Si3N4/Si) surfaces for nucleation and growth of large-area, uniform and ultrathin h-BN directly on Si3N4/Si substrates (B/N atomic ratio=1:1.11±0.09). Further, monolayer graphene van der Waals bonded with the produced h-BN surface benefits from h-BN's reduced roughness (3.4 times) in comparison to Si3N4/Si. Because the reduced surface roughness leads to reduction in surface roughness scattering and charge impurity scattering, therefore an enhanced intrinsic charge carrier mobility (3 folds) for graphene on h-BN/Si3N4/Si is found.

Abstract: Disclosed herein are boron-nitride nanoparticle membranes and methods of manufacturing boron-nitride nanoparticle membranes. In an embodiment, a boron-nitride nanoparticle membrane includes a matrix and a plurality of one-dimensional boron-nitride nanoparticles disposed within the matrix, where he plurality of boron-nitride nanoparticles are configured for selective molecular transport through each of the plurality of one-dimensional boron-nitride nanoparticles.

Abstract: A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN)XHy-radical interfacing with active sites on silicon nitride coated silicon (Si3N4/Si) surfaces for nucleation and growth of large-area, uniform and ultrathin h-BN directly on Si3N4/Si substrates (B/N atomic ratio=1:1.11±0.09). Further, monolayer graphene van der Waals bonded with the produced h-BN surface benefits from h-BN's reduced roughness (3.4 times) in comparison to Si3N4/Si. Because the reduced surface roughness leads to reduction in surface roughness scattering and charge impurity scattering, therefore an enhanced intrinsic charge carrier mobility (3 folds) for graphene on h-BN/Si3N4/Si is found.

Abstract: A method for depositing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate is provided. Due to the strong adhesion of graphene and cobalt to a semiconductor substrate, the layer of graphene is epitaxially deposited.

Abstract: A method for depositing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate is provided. Due to the strong adhesion of graphene and cobalt to a semiconductor substrate, the layer of graphene is epitaxially deposited.

Abstract: A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN)XHy-radical interfacing with active sites on silicon nitride coated silicon (Si3N4/Si) surfaces for nucleation and growth of large-area, uniform and ultrathin h-BN directly on Si3N4/Si substrates (B/N atomic ratio=1:1.11±0.09). Further, monolayer graphene van der Waals bonded with the produced h-BN surface benefits from h-BN's reduced roughness (3.4 times) in comparison to Si3N4/Si. Because the reduced surface roughness leads to reduction in surface roughness scattering and charge impurity scattering, therefore an enhanced intrinsic charge carrier mobility (3 folds) for graphene on h-BN/Si3N4/Si is found.

Abstract: A method for depositing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate is provided. Due to the strong adhesion of graphene and cobalt to a semiconductor substrate, the layer of graphene is epitaxially deposited.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.

Abstract: Graphene particulates, especially graphene nanoribbons (GNRs) and graphene quantum dots (GQDs), and a high-throughput process for the production of such particulates is provided. The graphene particulates are produced by a nanotomy process in which graphene blocks are cut from a source of graphite and then exfoliated into a plurality of graphene particulates. Graphene particulates having narrow widths, on the order of 100 nm or less, can be produced having band gap properties suitable for use in a variety of electrical applications.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.