Abstract: A system is provided for use with a DRAM, a DQS signal provider, a clock signal provider, a DQS line and a clock line. The DQS line can provide the DQS signal from the DQS signal provider to the DRAM. The clock line can provide the clock signal from the clock signal provider to the DRAM. The system includes a clock delay determining portion, a DQS delay determining portion, and adjustment portion and a controlling portion. The clock delay determining portion can determine a clock delay. The DQS delay determining portion can determine a DQS delay. The adjustment portion can generate an adjustment value based on the clock delay and the DQS delay. The controlling portion can instruct the DQS signal provider to adjust a time of providing a second DQS signal based on the adjustment value, wherein the clock delay is less than the DQS delay.

Abstract: Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.