Abstract: An embodiment of a semiconductor package apparatus may include technology to provide an entropy extractor including a physically unclonable function (PUF), a true random number generator (TRNG), an entropy source coupled to both the PUF and the TRNG, and a circuit to self-calibrate the entropy extractor. Other embodiments are disclosed and claimed.

Abstract: A Bitcoin mining hardware accelerator is described. A System on Chip implementing a Bitcoin mining hardware accelerator may include a processor core and a hardware accelerator coupled to the processor core, the hardware accelerator to mine digital currency. The hardware accelerator may include a first computational block, including a message digest datapath, wherein the first computational block is to: precompute a first summation of a 32-bit message (Wi), a 32-bit round constant (Ki), and a content of a first shifted state register (Gi?1), and store a result of the first summation in a state register (Hi). The Bitcoin mining hardware accelerator may further include a second computational block comprising a message scheduler datapath.

Abstract: Methods and apparatuses relating to high-performance authenticated encryption are described.

Abstract: The present disclosure provides a sensor system and method of operating the same. The sensor system includes a data collection mast including a base, a support member, a main member, a top plate, a first enclosure, a second enclosure, a first cantilever member, and a second cantilever member. The sensor system further includes a pair of stereoscopic cameras disposed on the main member extending through the second enclosure, a radar system disposed on the top plate, a compass disposed on the second cantilever member, a LIDAR unit disposed on the first cantilever member, and a control unit disposed on the main member within the first enclosure. Each of the pair of stereoscopic cameras, radar system, compass, and LIDAR unit are in electronic communication with the control unit, such that control unit receive the data collected from each sensor.

Abstract: An embodiment of a semiconductor package apparatus may include technology to provide an entropy extractor including a physically unclonable function (PUF), a true random number generator (TRNG), an entropy source coupled to both the PUF and the TRNG, and a circuit to self-calibrate the entropy extractor. Other embodiments are disclosed and claimed.

Abstract: Methods and apparatuses relating to a hashing accelerator having a frequency scaled message scheduler data path circuit are described.

Abstract: Embodiments disclosed herein include systems and methods for lane and object detection. A system may comprise a plurality of cameras and a processor in electronic communication with the cameras. The cameras may be disposed on a vehicle. The cameras may be configured to collect one or more images. The cameras may be configured to generate an image data feed using the one or more images. A method may comprise collecting one or more images; generating, from the one or more images, an image data feed; receiving, at a processor, the image data feed; and performing lane detection and object detection, and may employ a deep learning network.

Abstract: An object detection network can be trained with training images to identify and classify objects in images from a sensor system disposed on a maritime vessel. The objects in the images can be identified, classified, and heat maps can be generated. Instructions can be sent regarding operation of the maritime vessel. For some training images, water conditions, sky conditions, and/or light conditions in the image can be changed to generate a second image.

Abstract: The present disclosure provides a sensor system and method of operating the same. The sensor system includes a data collection mast including a base, a support member, a main member, a top plate, a first enclosure, a second enclosure, a first cantilever member, and a second cantilever member. The sensor system further includes a pair of stereoscopic cameras disposed on the main member extending through the second enclosure, a radar system disposed on the top plate, a compass disposed on the second cantilever member, a LIDAR unit disposed on the first cantilever member, and a control unit disposed on the main member within the first enclosure. Each of the pair of stereoscopic cameras, radar system, compass, and LIDAR unit are in electronic communication with the control unit, such that control unit receive the data collected from each sensor.

Abstract: Disclosed herein are systems, methods, and apparatuses for deep learning and intelligent sensing system integrations. A processor may be configured to receive a plurality of images from the sensor system, identify objects in the images in an offline mode, classify the objects in the images in the offline mode, generate heat maps in the offline mode, and send instructions regarding operation of the maritime vessel based on the objects that are identified. The visual sensor may be a stereoscopic camera. The processor may be further configured to perform stereoscopy. The instructions may include a speed or a heading of, for example, a maritime vessel.

Abstract: Disclosed embodiments relate to a unified Advanced Encryption Standard (AES), SMS4, and Camellia (CML) accelerator. In one example, a processor includes fetch circuitry to fetch a cipher instruction specifying an opcode, a datum, and a key, the opcode to specify one of three cryptographic modes and an operation, decode circuitry to decode the fetched cipher instruction, and execution circuitry to respond to the decoded cipher instruction by performing the operation using a selected one of three block ciphers corresponding to the specified cryptographic mode and a unified cipher datapath shared by the three block ciphers, the unified cipher datapath comprising a plurality of hybrid substitution boxes (Sboxes) to perform Galois Field (GF) multiplications and inverse computations, wherein the unified cipher datapath is to implement an eighth-order polynomial isomorphically equivalent to each polynomial used by the three block ciphers by calculating and then combining two fourth-order polynomials.

Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.

Abstract: In one example an apparatus comprises accelerator logic to pre-compute at least a portion of a message representative, hash logic to generate the message representative based on an input message, and signature logic to generate a signature to be transmitted in association with the message representative, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and determine whether the message representative satisfies a target threshold allocation of computational costs between a cost to generate the signature and a cost to verify the signature. Other examples may be described.

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.

Abstract: In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.

Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.

Abstract: A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments, according to one embodiment. A method of embodiments, as described herein, includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.

Abstract: An apparatus is provided which comprises: an entropy source to produce a first random sequence of bits, wherein the entropy source comprises an array of bi-stable cross-coupled inverter cells; a first circuitry coupled to the entropy source, wherein the first circuitry to generate an entropy source selection set; and a second circuitry coupled to the entropy source and the first circuitry, wherein the second circuitry is to receive the first random sequence and the entropy source selection set, and wherein the second circuitry is to generate a second random sequence.