Abstract: There is provided a semiconductor package and method for fabricating the same.

Abstract: A heat slug or spreader is attached directly to a surface of the die in a ball grid array (BGA) package. The heat spreader roughly conforms to the topological profile of the die, underlying substrate, and electrical interconnections between the die and the substrate, such as bond wires. The outer portion of the heat spreader substantially cover the outer portion of the substrate, or alternatively, cover only those portions extending in laterally from the sides of the chip and not the corners. An encapsulant completely covers the heat spreader and die.

Abstract: A stackable semiconductor package includes a substrate having a first surface, an opposite second surface, and through hole. Circuit patterns on the first and second surfaces of the substrate include lands, and the circuit patterns of the second surface also include bond fingers. A semiconductor chip is in the throughhole. The semiconductor chip has bond pads, which are oriented in a same direction as the second surface of the substrate. Wires electrically connect the bond pads to the bond fingers. An encapsulant fills the through hole and covers the semiconductor chip, the wires and the bond fingers, without covering the lands. Conductive balls are fused to the lands of the first surface of the substrate. A second semiconductor package may be stacked on the second surface of the substrate, and conductive balls of the second semiconductor package may be fused to the lands of the second surface.

Abstract: A semiconductor package and method for fabricating the same is disclosed. In one embodiment, the semiconductor package includes a circuit board, at least two semiconductor chips, electric connection means, an encapsulant, and a plurality of conductive balls. The circuit board has a resin layer and a circuit pattern. The resin layer is provided with an opening at its center portion. The circuit pattern is formed on at least one of upper and lower surfaces of the resin layer and includes one or more bond fingers and ball lands exposed to the outside. The semiconductor chips have a plurality of input/output pads on an active surface thereof. The semiconductor chips are stacked at a position of the opening of the circuit board, with at least one of the chips being within the opening. Alternatively, both chips are in the opening. The electric connection means connects the input/output pads of the semiconductor chips to the bond fingers of the circuit board.

Abstract: A semiconductor package and method for fabricating the same is disclosed. In one embodiment, the semiconductor package includes a circuit board, at least two semiconductor chips, electric connection means, an encapsulant, and a plurality of conductive balls. The circuit board has a resin layer and a circuit pattern. The resin layer is provided with an opening at its center portion. The circuit pattern is formed on at least one of upper and lower surfaces of the resin layer and includes one or more bond fingers and ball lands exposed to the outside. The semiconductor chips have a plurality of input/output pads on an active surface thereof. The semiconductor chips are stacked at a position of the opening of the circuit board, with at least one of the chips being within the opening. Alternatively, both chips are in the opening. The electric connection means connects the input/output pads of the semiconductor chips to the bond fingers of the circuit board.

Abstract: A semiconductor package and method for manufacturing the same is disclosed. The semiconductor package comprises a semiconductor chip, a circuit board, an electrical connection means, an encapsulation material and a plurality of conductive balls. The semiconductor chip has a first surface and a second surface. A plurality of input and output pads are formed on one of the first and second surfaces. The circuit board comprises a thin film having a first surface and a second surface and being provided with a center hole in which the semiconductor chip is positioned, a plurality of circuit patterns being formed on the first surface of the thin film and including a plurality of bond fingers and ball lands, and a cover coat covering the circuit board except for the bond fingers and the ball lands. The electric connection means electrically connects the input and output pads of the semiconductor chip with the bond fingers of the circuit board.

Abstract: A semiconductor package and method for fabricating the same is disclosed. In one embodiment, the semiconductor package includes a circuit board, at least two semiconductor chips, electric connection means, an encapsulant, and a plurality of conductive balls. The circuit board has a resin layer and a circuit pattern. The resin layer is provided with an opening at its center portion. The circuit pattern is formed on at least one of upper and lower surfaces of the resin layer and includes one or more bond fingers and ball lands exposed to the outside. The semiconductor chips have a plurality of input/output pads on an active surface thereof. The semiconductor chips are stacked at a position of the opening of the circuit board, with at least one of the chips being within the opening. Alternatively, both chips are in the opening. The electric connection means connects the input/output pads of the semiconductor chips to the bond fingers of the circuit board.

Abstract: Semiconductor packages having a thin structure capable of easily discharging heat from a semiconductor chip included therein, and methods for fabricating such semiconductor packages, are disclosed.

Abstract: There is provided a semiconductor package and method for fabricating the same.

Abstract: Semiconductor packages having a thin structure capable of easily discharging heat from a semiconductor chip included therein, and methods for fabricating such semiconductor packages, are disclosed.

Abstract: A multiple chip package and method of making the package allow multiple same size or different size chips to be stacked over each other, thereby creating a thin profile multi-chip package. Chips are attached to one surface of a continuous flexible substrate. The substrate has a metallization layer, which is electrically connected to the chips, such as via bond wires attached to center bond pads of the chips and to bond fingers on the metallization layer. Interconnections, such as solder balls, are attached to the other surface of the substrate and only at the portion opposite to the first chip. The substrate is folded to bring the first chip toward a second chip, which are then attached, such as with an insulative adhesive spacer. If any additional chips remain on the substrate, the substrate is folded to sequentially bring each additional chip toward the surface of the substrate opposite to the preceding chip and is secured thereto.

Abstract: A semiconductor package and method for fabricating the same is disclosed. In one embodiment, the semiconductor package includes a circuit board, at least two semiconductor chips, electric connection means, an encapsulant, and a plurality of conductive balls. The circuit board has a resin layer and a circuit pattern. The resin layer is provided with an opening at its center portion. The circuit pattern is formed on at least one of upper and lower surfaces of the resin layer and includes one or more bond fingers and ball lands exposed to the outside. The semiconductor chips have a plurality of input/output pads on an active surface thereof. The semiconductor chips are stacked at a position of the opening of the circuit board, with at least one of the chips being within the opening. Alternatively, both chips are in the opening. The electric connection means connects the input/output pads of the semiconductor chips to the bond fingers of the circuit board.

Abstract: A method for fabricating LGA-, LCCY- and BGA-types of very thin, chip size semi-conductor packages (“VCSP's”) includes substantially reducing the thickness of a semiconductor wafer containing the semiconductor chips to be packaged by grinding and/or etching the wafer from its back side prior to singulation of the chips from the wafer. The thinned-down chips thus produced are electrically connected to corresponding insulative substrates contained in an integral array thereof using the “flip chip” interconnection method. The narrow row space between the chips and the substrates are sealed with an underfill material, and the individual, finished VCSP's are then singulated from the array.

Abstract: This invention provides a method for making a semiconductor package with stacked dies that eliminates fracturing of the upper die(s) during the wire bonding process. One embodiment of the method includes the provision of a substrate and pair of semiconductor dies, each having opposite top and bottom surfaces and a plurality of wire bonding pads around the peripheries of their respective top surfaces. One die is attached and wire bonded to a top surface of the substrate. A measured quantity of an uncured, fluid adhesive is dispensed onto the top surface of the first die, and the adhesive is squeezed toward the edges of the dies by pressing the bottom surface of the second die down onto the adhesive until the two dies are separated by a layer of the adhesive. The adhesive is cured, the second die is then wire bonded to the substrate, and the dies are then molded over with an encapsulant.

Abstract: Alternative methods for making memory cards for computers and such eliminate a need for a separate external housing and a separate chip encapsulation step and enable more memory to be packaged in a same-sized card. One of said methods includes providing a substrate having opposite first and second surfaces with a memory chip mounted on and in electrical connection with a first surface of said substrate. Said second surface of said substrate is temporarily attached to a first surface of a flat carrier sheet, e.g., an adhesive tape. In one embodiment, a mold having a cavity therein is placed on said first surface of said carrier sheet such that said chip and said first surface of said substrate are enclosed in said cavity between said mold and said carrier sheet. A fluid plastic is introduced into said cavity and cured to encapsulate said chip and at least said first surface of said substrate in a protective, monolithic body of hardened plastic. A completed card is then detached from said carrier sheet.

Abstract: A method is disclosed for manufacturing chip-scale semiconductor packages at a wafer-scale level using wafer mapping techniques. In the method, a semiconductor wafer and/or a circuit substrate, each respectively comprising a plurality of individual chips and circuit pattern units, is/are pre-tested and discriminated in terms of the quality and/or grade of each individual chip unit and/or circuit pattern unit contained therein. The test results are marked on the lower surface of each chip unit and/or on each pattern unit. The substrate is laminated to the wafer to form a laminated assembly prior to performing the packaging process, which typically includes a wire bonding step, an encapsulation step and a solder ball welding step. A plurality of connected package units are thereby formed in the laminated substrate-wafer assembly. The package units are then singulated from each other and the laminated assembly by a cutting process.

Abstract: Chip-size semiconductor packages (“CSPs”) containing multiple stacked dies are disclosed. The dies are mounted on one another in a stack such that corresponding ones of the vias in the respective dies are coaxially aligned. An electrically conductive wire or pin is in each set of aligned vias and soldered to corresponding ones of the terminal pads. The pins include portions protruding from the stack of dies that serve as input-output terminals of the package. Heat spreaders can be interleaved between the stacked dies to enhance heat dissipation from the package.

Abstract: There is provided a semiconductor package and method for fabricating the same.

Abstract: Embodiments of integrated circuit packages for housing a plurality of integrated circuits are disclosed, along with methods of making the packages. One embodiment of a package includes a substrate having a first surface with first metallizations thereon and an opposite second surface with second metallizations thereon. One or more apertures extend through the substrate between the first and second surfaces. Conductive vias also extend through the substrate. Eachof the vias electrically connect one or more of the first and second metallizations. A first integrated circuit having a first surface with first bond pads thereon and an opposite second surface is attached to the second surface of the substrate so that the first bond pads are superimposed with an aperture. At least one second integrated circuit is attached to the second surface of the first integrated circuit. An opposite surface of the second integrated circuit has edge bond pads thereon.

Abstract: A semiconductor package incorporates spacer strips enabling one or more semiconductor dies having central terminal pads to be stacked on top of one another within the package and reliably wire bonded to an associated substrate without shorting of the bonded wires. Each of the spacer strips comprises a flat, elongated strip of an insulative material that mount at edges of a surface of a die such that they straddle the central terminal pads thereon. The die is electrically connected to the substrate by a plurality of fine conductive wires having a first end bonded to one of the central terminal pad on the die, a second end bonded to a terminal pad on the substrate, and an intermediate portion between the first and second ends that passes transversely across the top surface of one of the spacer strips. The spacer strips have spaced pads or grooves on or in their top surfaces that captivate the individual wires and thereby redistribute the wires and prevent them from contacting the die and each other.