Abstract: A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal.

Abstract: A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal.

Abstract: An improved data recovery circuit based on an oversampling technique to select the best data sample to be kept as the data to recover that is only based on accumulating the data edges (or transitions). The incoming serial data stream with jitter is oversampled in an oversampling circuit by means of the multiple phases of a reference clock (clk) to produce data samples. Each sample is compared to the sample(s) collected with the next clock phase(s) in an edge detector circuit to determine the presence of a data edge and the edge information is stored and accumulated in a data edge memory. A selection determination circuit uses the memorized edge information to indicate which sample is the farthest from the data edges. A selection validation circuit validates the selection to avoid false determination due to jitter and skew.

Abstract: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Abstract: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Abstract: A data recovery circuit employing an oversampling technique. The incoming serial data stream with jitter is oversampled by means of the multiple phases of a reference clock to produce data samples. Each sample is compared to the samples collected with the next clock phase in an edge detector circuit to determine the presence of a data edge. The edge information, representative of the data edge positions, is stored and accumulated in the form of a bit map. A detection/suppression circuit detects and suppresses edges which are not adjacent to any other edge in the edge memory. A selection determination circuit uses the edge information to indicate which sample is the farthest from the data edges. A selection validation circuit validates the selection to avoid false determination due to jitter and skew.

Abstract: An improved data recovery circuit based on an oversampling technique to select the best data sample to be kept as the data to recover that is only based on accumulating the data edges (or transitions). The incoming serial data stream with jitter is oversampled in an oversampling circuit by means of the multiple phases of a reference clock (clk) to produce data samples. Each sample is compared to the sample(s) collected with the next clock phase(s) in an edge detector circuit to determine the presence of a data edge and the edge information is stored and accumulated in a data edge memory. A selection determination circuit uses the memorized edge information to indicate which sample is the farthest from the data edges. A selection validation circuit validates the selection to avoid false determination due to jitter and skew.

Abstract: An improved data recovery circuit based on an oversampling technique to select the best data sample to be kept as the data to recover that is only based on accumulating the data edges (or transitions). The incoming serial data stream with jitter is oversampled in an oversampling circuit by means of the multiple phases of a reference clock (clk) to produce data samples. Each sample is compared to the sample(s) collected with the next clock phase(s) in an edge detector circuit to determine the presence of a data edge and the edge information is stored and accumulated in a data edge memory. A selection determination circuit uses the memorized edge information to indicate which sample is the farthest from the data edges. A selection validation circuit validates the selection to avoid false determination due to jitter and skew.

Abstract: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Abstract: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Abstract: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Abstract: A transition detection, validation and memorization (TDVM) circuit detects the position of a transition in a stream of serially transmitted binary data (bits) that are over sampled and generates a control signal indicating which sampled signal represents the best data. The incoming data stream is over sampled by the n phases of a multiple phase clock signal. Then n over sampled signals are fed into the TDVM circuit which includes a first section for detecting the transition at the positions of two consecutive sampled signals according to a specific signal processing, a second section for validating the transition position, and a third section for memorizing the validated transition position and generating a control signal that is used to recover the data.

Abstract: There is disclosed a data recovery (DR) circuit including an over sampling (OS) circuit, a transition detection (TD) circuit and a sample selection/data alignment (SSDA) circuit. A multiphase clock generating circuit delivering n phases is coupled to each of these circuits. The OS circuit over samples the received digital data stream and produces n sampled signals at each clock period. The TD circuit is configured to detect a data transition (if any) and to generate n select signals, only one of which is active and represents a determined delay with respect to the transition position, indicating thereby which over sampled signal is the best to be retained. The SSDA circuit is configured to generate the recovered (retimed) data signal that is aligned with a predefined phase of the multiphase clock signal. The data recovery circuit is well adapted to high speed serial data communications between integrated circuits/systems on digital networks.

Abstract: There is disclosed a sample selection and data alignment circuit that is able to recover (retime) a data on a predefined phase of a multiphase clock signal. A plurality of over sampled signals (G0, . . . , Gn?1) is obtained by over sampling an incoming serial binary data (bits) stream with the n phases (G0, . . . , Gn?1) of a multiphase clock signal. A reliable over sampled signal is selected according to a selected signal (G0, . . . , Gn?1) generated by an edge detector which designates which over sampled signal is the best for subsequent processing.

Abstract: An improved data recovery circuit based on an oversampling technique to select the best data sample to be kept as the data to recover that is only based on accumulating the data edges (or transitions). The incoming serial data stream with jitter is oversampled in an oversampling circuit by means of the multiple phases of a reference clock (clk) to produce data samples. Each sample is compared to the sample(s) collected with the next clock phase(s) in an edge detector circuit to determine the presence of a data edge and the edge information is stored and accumulated in a data edge memory. A selection determination circuit uses the memorized edge information to indicate which sample is the farthest from the data edges. A selection validation circuit validates the selection to avoid false determination due to jitter and skew.

Abstract: A data recovery circuit employing an oversampling technique. The incoming serial data stream with jitter is oversampled by means of the multiple phases of a reference clock to produce data samples. Each sample is compared to the samples collected with the next clock phase in an edge detector circuit to determine the presence of a data edge. The edge information, representative of the data edge positions, is stored and accumulated in the form of a bit map. A detection/suppression circuit detects and suppresses edges which are not adjacent to any other edge in the edge memory. A selection determination circuit uses the edge information to indicate which sample is the farthest from the data edges. A selection validation circuit validates the selection to avoid false determination due to jitter and skew.

Abstract: An improved data recovery circuit based on an oversampling technique wherein intersymbol interference (ISI) is compensated. A detection circuit is connected at the output of a conventional recovery circuit. The recovered data is applied to the detection circuit which includes flip-flops to memorize the previous state of the recovered data when no data transition is detected within a predefined number of clock periods. The detection circuit detects sequences of a predetermined number of consecutive identical bits which indicates the presence of ISI. It generates a feedback signal that is applied to the decision circuit and to the data sample selection circuit to shift the selection of a data sample of one position to compensate ISI.

Abstract: A built-in self test system for testing a clock and data recovery circuit. The present invention provides a built-in self test circuit which operates with high speed phase lock loop. The built-in circuit comprises data generating means for generating a test data byte and serializing means coupled to the data generating means for converting the test data byte into serial test data. The clock and data recovery means are coupled to the output of the serializing means for recovering the clock and test data from the serial test data. A deserializing means coupled to the output of the clock and data recovery means converts the recovered serial test data into a recovered test data byte, and analyzing means connected to the output of the deserializing means compares the recovered test data byte to the initial test data byte.

Abstract: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Abstract: There is disclosed a sample selection and data alignment circuit that is able to recover (retime) a data on a predefined phase of a multiphase clock signal. A plurality of over sampled signals (SO, . . . , Sn−1) is obtained by over sampling an incoming serial binary data (bits) stream with the n phases (C0, . . . , Cn−1) of a multiphase clock signal. A reliable over sampled signal is selected according to a select signal (G0. . . , Gn−1) generated by an edge detector which designates which over sampled signal is the best for subsequent processing. In essence, the circuit comprises a plurality of n substantially identical logic blocks. The first logic block includes a latch receiving sampled signal So on its data input and the phase clock signal C0 on its clock input. Each other logic block, e.g. logic block i, further includes a multiplexer having two inputs, the first input is connected to the output of the latch of the preceding logic block and the second input receives sampled signal Si.