Abstract: In one aspect, a method for NOR flash cell-array programming in a neural circuit includes the step of erasing a cell array. The method includes the step of programming a set of reference cells of a reference cell array to a target reference threshold voltage (Vt_ref). The method includes the step of generating, with the reference cells, a current or voltage, reference signal. The method includes the step of using the reference signal to bias the neural cells during verification of program state of the neural cells to achieve their respective target threshold voltages (Vt_cell). The method includes the step of programming a set of neural cells of a neural cell array to their respective target threshold voltages.

Abstract: Memory having an array of memory cells might include control logic configured to cause the memory to inhibit memory cells of a first subset of memory cells from programming during each programming pulse of a first plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of a second plurality of programming pulses, inhibit memory cells of a second subset of memory cells from programming during each programming pulse of the second plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of the first plurality of programming pulses, and enable memory cells of a third subset of memory cells for programming during at least one programming pulse of the first plurality of programming pulses and during at least one programming pulse of the second plurality of programming pulses.

Abstract: Method of operating a memory include increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses, and subsequently increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses, wherein the first plurality of programming pulses have respective voltage levels within a first range of voltage levels, the second plurality of programming pulses have respective voltage levels within a second range of voltage levels, and a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.

Abstract: In one aspect, A method for computing neural network computation includes the step of, providing plurality of neurons, coupled with a plurality of inputs, through a plurality of synapses. Each neuron output is given by an equation ?(Xi*Yi)+b. Xi*Yi comprises the ith synapse of the neuron. Xi comprises a set of Xi input vectors. Each Xi input vector is translated into an equivalent electrical signal for an ith corresponding synapse of the plurality of neurons, Yi comprises a set of Yi weight vectors, wherein each Yi weight vector comprises a parameter for the ith corresponding synapse of the plurality of neurons. Each synapse is a sub-system and the sub-system comprises a negative vector neural circuit, a positive vector neural circuit, and a set of four non-volatile memory weight cells for computation. The method includes the step of identifying the input vector x as a positive input vector or a negative input vector.

Abstract: In one aspect, a method of a neuron circuit includes the step of providing a plurality of 2N?1 single-level-cell (SLC) flash cells for each synapse (Yi) connected to a bit line forming a neuron. The method includes the step of providing an input vector (Xi) for each synapse Yi wherein each input vector is translated into an equivalent electrical signal ESi (current IDACi, pulse, TPULSEi, etc). The method includes the step of providing an input current to each synapse sub-circuit varying from 20*ESi to (2N?1)*ESi. The method includes the step of providing a set of weight vectors or synapse (Yi), wherein each weight vector is translated into an equivalent threshold voltage level or resistance level to be stored in one of many non-volatile memory cells assigned to each synapse (Yi).

Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programming a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

Abstract: Method of operating a memory include increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses, and subsequently increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses, wherein the first plurality of programming pulses have respective voltage levels within a first range of voltage levels, the second plurality of programming pulses have respective voltage levels within a second range of voltage levels, and a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.

Abstract: Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.

Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

Abstract: Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.

Abstract: Memories having a plurality of cell pairs, where each cell pair of the plurality of cell pairs is programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in a memory are useful in mitigating match errors, such as in a CAM (Content Addressable Memory) memory device.

Abstract: A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programing the first memory cell to the first level. After programing the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programing the second memory cell to the second level.

Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.

Abstract: A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programing the first memory cell to the first level. After programing the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programing the second memory cell to the second level.

Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.

Abstract: A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programming the first memory cell to the first level. After programming the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programming the second memory cell to the second level.

Abstract: Methods for managing data stored in a memory device facilitate managing utilization of memory of different densities. The methods include reading first data from a first number of pages or blocks of memory cells having a first density, performing a data handling operation on the read first data to generate second data, and writing the second data to a second number of pages or blocks of memory cells having a second density, wherein the second density is different than the first density, and wherein the second number is different than the first number.