Patents by Inventor Vishal Sarin

Vishal Sarin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SENSING MEMORY CELLS
    Publication number: 20140098607
    Abstract: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 10, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung Sheng Hoei, Frankie Roohparvar, Giulio-Giuseppe Marotta
  • Memory controller self-calibration for removing systemic influence
    Patent number: 8693246
    Abstract: Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: April 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei
  • Analog sensing of memory cells with a source follower driver in a semiconductor memory device
    Patent number: 8687430
    Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Programming methods and memories
    Patent number: 8687431
    Abstract: Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, William H. Radke, Frankie F. Roohparvar
  • Fast start charge pump for voltage regulators
    Patent number: 8674749
    Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: March 18, 2014
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sang Thanh Nguyen, Anh Ly, Hung Q. Nguyen, Wingfu AAron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang
  • PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL
    Publication number: 20140053033
    Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
    Type: Application
    Filed: October 17, 2013
    Publication date: February 20, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • METHOD FOR KINK COMPENSATION IN A MEMORY
    Publication number: 20140043912
    Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
    Type: Application
    Filed: October 3, 2013
    Publication date: February 13, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Violante Moschiano, Frankie Roohparvar, Giovanni Santin, Vishal Sarin, Allahyar Vahidimowlavi, Tommaso Vali
  • REFRESH OF NON-VOLATILE MEMORY CELLS BASED ON FATIGUE CONDITIONS
    Publication number: 20140040683
    Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.
    Type: Application
    Filed: October 4, 2013
    Publication date: February 6, 2014
    Applicant: Mocron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • Cell deterioration warning apparatus and method
    Patent number: 8644070
    Abstract: Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Warning of cell deterioration can be performed using reference cells programmed in accordance with a known pattern such as to approximate deterioration of non-volatile memory cells of the device.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: February 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Sensing operations in a memory device
    Patent number: 8611156
    Abstract: Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: December 17, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan Pabustan, Vishal Sarin, Dzung H. Nguyen
  • Programming based on controller performance requirements
    Patent number: 8611149
    Abstract: A solid state drive is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, including an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: December 17, 2013
    Assignee: Micron Technology
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • REDUCING NOISE IN SEMICONDUCTOR DEVICES
    Publication number: 20130301357
    Abstract: The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage.
    Type: Application
    Filed: July 16, 2013
    Publication date: November 14, 2013
    Inventors: Vishal Sarin, Frankie Roohpavar, Hoei Jung Sheng
  • Reducing effects of program disturb in a memory device
    Patent number: 8582357
    Abstract: The programming disturb effects in a semiconductor non-volatile memory device can be mitigated by biasing unselected memory cells with a negative voltage while a well containing the memory cells receives a positive voltage. A selected memory cell in the well can be biased with a negative voltage while the well is at the positive voltage then the selected memory cell bias transitions to a positive programming voltage when the well returns to a ground potential.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: November 12, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Vishal Sarin
  • Programming error correction code into a solid state memory device with varying bits per cell
    Patent number: 8578244
    Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: November 5, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • METHOD AND APPARATUS FOR READING DATA FROM NON-VOLATILE MEMORY
    Publication number: 20130286745
    Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC).
    Type: Application
    Filed: June 27, 2013
    Publication date: October 31, 2013
    Inventors: Frankie Roohparvar, Vishal Sarin, William Radke
  • Sensing memory cells
    Patent number: 8565024
    Abstract: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: October 22, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jung Sheng Hoei, Giulio-Giuseppe Marotta
  • ANALOG SENSING OF MEMORY CELLS WITH A SOURCE FOLLOWER DRIVER IN A SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20130272070
    Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.
    Type: Application
    Filed: June 17, 2013
    Publication date: October 17, 2013
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Rooparvar
  • Method for kink compensation in a memory
    Patent number: 8553461
    Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: October 8, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Frankie Roohparvar, Giovanni Santin, Vishal Sarin, Allahyar Vahidimowlavi, Tommaso Vali
  • Configurable digital and analog input/output interface in a memory device
    Patent number: 8526243
    Abstract: Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad. One of the two paths on each pad is selected in response to command signals that indicate the nature of the signal being either transmitted to the device or read from the device. Each digital path includes a latch for latching digital input data. Each analog path includes a sample/hold circuit for storing either analog data being read from or analog data being written to the memory device.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: September 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei
  • Fast voltage regulators for charge pumps
    Patent number: 8497667
    Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: July 30, 2013
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sang Thanh Nguyen, Anh Ly, Hung Q. Nguyen, Wingfu Aaron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang