Patents by Inventor Vishnu K. Agarwal

Vishnu K. Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8120083
    Abstract: Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode structures separated by a gap; and a polymer-based ferroelectric layer overlying and directly abutting some of the electrode structures. Methods may comprise actions to form and operate the apparatus and systems. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: February 21, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishnu K. Agarwal, Howard E. Rhodes
  • Patent number: 8111965
    Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: February 7, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
  • Publication number: 20110206332
    Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.
    Type: Application
    Filed: May 2, 2011
    Publication date: August 25, 2011
    Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtel Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
  • Patent number: 7936955
    Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: May 3, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
  • Publication number: 20100290265
    Abstract: Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode structures separated by a gap; and a polymer-based ferroelectric layer overlying and directly abutting some of the electrode structures. Methods may comprise actions to form and operate the apparatus and systems. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: July 30, 2010
    Publication date: November 18, 2010
    Inventors: Vishnu K. Agarwal, Howard E. Rhodes
  • Publication number: 20100220958
    Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.
    Type: Application
    Filed: May 14, 2010
    Publication date: September 2, 2010
    Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
  • Patent number: 7768049
    Abstract: Integrated memory circuits, key components in thousands of electronic and computer products, have been made using ferroelectric materials, which offer faster write cycles and lower power requirements than some other materials. However, the present inventors have recognized, for example, that conventional techniques for working with the polymers produce polymer layers with thickness variations that compromise performance and manufacturing yield. Accordingly, the present inventors devised unique methods and structures for polymer-based ferroelectric memories. One exemplary method entails forming an insulative layer on a substrate, forming two or more first conductive structures, with at least two of the first conductive structures separated by a gap, forming a gap-filling structure within the gap, and forming a polymer-based ferroelectric layer over the gap-filling structure and the first conductive structures. In some embodiments, the gap-filling structure is a polymer, a spin-on-glass, or a flow-fill oxide.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: August 3, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Vishnu K. Agarwal, Howard E. Rhodes
  • Patent number: 7720341
    Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: May 18, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
  • Patent number: 7548667
    Abstract: The present technique relates to a device including an optical integrated circuit amplifier and another type of optical integrated circuit. The optical integrated circuit amplifiers and other optical integrated circuits are coupled together through optical paths. The optical integrated circuit amplifiers and other optical integrated circuits of the optical components are fabricated on the same substrate. The optical integrated circuit amplifiers and other optical integrated circuit amplifiers maybe fabricated on different levels of the same substrate.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: June 16, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Vishnu K. Agarwal
  • Patent number: 7508074
    Abstract: In accordance with one embodiment of the present invention, a semiconductor structure is provided comprising a poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly. The present invention also relates to a memory cell array comprising an array of wordlines and digitlines arranged to access respective memory cells within the array. Respective wordlines comprise a poly-metal stack formed over a semiconductor substrate in accordance with the present invention. Additionally, the present invention relates to a computer system comprising a memory cell array of the present invention.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: March 24, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Vishnu K. Agarwal
  • Patent number: 7508075
    Abstract: A semiconductor structure is provided comprising a self-aligned poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly-metal stack. A semiconductor structure is also provided where an etch stop layer is present in the poly region of the poly-metal stack. The present invention also relates more broadly to a memory cell array and a computer system including the poly-metal stack of the present invention.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: March 24, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Vishnu K. Agarwal
  • Patent number: 7491602
    Abstract: Systems, devices, structures, and methods are described that inhibit atomic migration that creates an open contact between a metallization layer and a conductive layer of a semiconductor structure. A layer of an inhibiting substance may be used to inhibit a net flow of atoms so as to maintain conductivity between the metallization layer and the conductive layer of the semiconductor structure. Such layer of inhibiting substance acts even with the presence of point defects for a given temperature.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: February 17, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Vishnu K. Agarwal
  • Patent number: 7488665
    Abstract: Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which are mechanical reinforcement against shear forces and the like, by a brace layer that transversely extends between lateral sides of at least two of the free-standing microstructures. The brace layer is formed as a microbridge type structure spanning between the upper ends of the two or more microstructures.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: February 10, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Vishnu K. Agarwal, Gurtej Sandhu
  • Patent number: 7446363
    Abstract: The invention comprises integrated circuitry and to methods of forming capacitors. In one implementation, integrated circuitry includes a capacitor having a first capacitor electrode, a second capacitor electrode and a high K capacitor dielectric region received therebetween. The high K capacitor dielectric region has a high K substantially amorphous material layer and a high K substantially crystalline material layer. In one implementation, a capacitor forming method includes forming a first capacitor electrode layer over a substrate. A substantially amorphous first high K capacitor dielectric material layer is deposited over the first capacitor electrode layer. The substantially amorphous high K first capacitor dielectric material layer is converted to be substantially crystalline. After the converting, a substantially amorphous second high K capacitor dielectric material layer is deposited over the substantially crystalline first high K capacitor dielectric material layer.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: November 4, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Vishnu K. Agarwal
  • Publication number: 20080226247
    Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 18, 2008
    Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
  • Patent number: 7390712
    Abstract: Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: June 24, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Vishnu K. Agarwal, Dan Gealy
  • Patent number: 7359607
    Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: April 15, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
  • Patent number: 7288808
    Abstract: A capacitor fabrication method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer. The method may further include forming rugged polysilicon over the substrate, the first electrode being over the rugged polysilicon. Accordingly, the outer surface area of the first electrode can be at least 30% greater than the outer surface area of the substrate without the first electrode including polysilicon.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: October 30, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Vishnu K. Agarwal, Garry A. Mercaldi
  • Patent number: 7282756
    Abstract: Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which are mechanical reinforcement against shear forces and the like, by a brace layer that transversely extends between lateral sides of at least two of the free-standing microstructures. The brace layer is formed as a microbridge type structure spanning between the upper ends of the two or more microstructures.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: October 16, 2007
    Assignee: Micron Technology Inc.
    Inventors: Vishnu K. Agarwal, Gurtej Sandhu
  • Patent number: 7282666
    Abstract: A material processing system and method is disclosed for processing materials such as amorphous silicon in an annealing processes and lithography processes on a silicon wafer, as well as ablation processes. A first laser generates periodic pulses of radiation along a beam path directed at the target material. Similarly, at least one additional laser generates periodic pulses. A beam aligner redirects the beam path of the at least one laser, such that the beam from the at least one additional laser is directed at the target along a path colinear with the first laser's beam path. As a result, all the lasers are directed at the target along the same combined beam path. The periodic pulses of the at least one additional laser are delayed relative to the first laser such that multiple pulses impinge on the target within a single pulse cycle of any given laser.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: October 16, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Vishnu K. Agarwal, William A. Stanton