Abstract: A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.

Abstract: An electrostatic discharge (ESD) protection circuit includes a control circuit configured to generate a signal indicating whether an input voltage on an input/output pad is excessive. The protection circuit also includes a voltage divider configured to receive the signal from the control circuit and to divide the input voltage to produce a divided voltage. The protection circuit further includes an inverter chain having multiple inverters, where a first inverter is configured to receive the divided voltage and at least two inverters are configured to generate transistor control signals. In addition, the protection circuit includes a plurality of transistors configured to receive the transistor control signals and, when the input voltage is excessive, to prevent the input voltage from being provided to a protected circuit.

Abstract: In an LVTSCR, an avalanche diode based control circuit controls both the base of the internal PNP of the LVTSCR as well as the gate of the LVTSCR.

Abstract: In a silicon-based light emitting diode-photodiode (LED-PD) arrangement, the LED is implemented as an avalanche LED (ALED) and the ALED and PD are integrated into a common integrated circuit. The ALED is formed around a cross-shaped PD and is separated from the PD by a deep trench region. In order to create current crowding close to the deep trench the ALED includes an NBL or PBL having a narrowing at its end.

Abstract: In an SCR ESD protection circuit, the n-type emitter of the SCR is controlled to receive electron current only during an ESD event, thereby defining PNP characteristics during normal operation and SCR characteristics during an ESD event.

Abstract: In an ESD clamp formed in a SOI process, voltage tolerance is increased by introducing multiple blocking junctions between the anode and cathode of the device.

Abstract: In a dual direction ESD protection circuit formed from multiple base-emitter fingers that include a SiGe base region, and a common sub-collector region, the I-V characteristics are adjusted by including P+ regions to define SCR structures that are operable to sink positive and negative ESD pulses, and adjusting the layout and distances between regions and the number of regions.

Abstract: In a power device such as an NLDMOS power array comprising multiple NLDMOS devices, the gates of which are driven by a driver, self protection against overvoltage events is implemented by providing a high side pull-up avalanche diode connected to at least some of the gates of the NLDMOS devices.

Abstract: In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.

Abstract: In a high voltage ESD protection structure with a gate voltage reference and low impedance load, the CDM robustness of the structure is improved by including a gate resistor and a reverse path diode.

Abstract: In the case of adjacent high voltage nodes in which one node is protected by a lateral BJT clamp, the irreversible burnout due to transient latch-up between the two adjacent high voltage pins of the structure is avoided by increasing the base contact region by including a sinker connected to the base.

Abstract: A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators.

Abstract: In an NLDMOS array, the source fingers are terminated by p+ Pbody diffusions or Pbody diffusions. The drain-source spacing is reduced by arranging p+ Pbody regions for contacting the Pbody, in line with n+ source regions to define source fingers with interdigitated p+ Pbody regions.

Abstract: In a silicon-based light emitting diode-photodiode (LED-PD) arrangement, the LED is implemented as an avalanche LED (ALED) and the ALED and PD are integrated into a common integrated circuit. The ALED is formed around a cross-shaped PD and is separated from the PD by a deep trench region.

Abstract: In an active clamp implemented in a 5V complementary BiCMOS process, the footprint of the active clamp, which includes at least one NMOS clamp stack, is reduced by introducing a BJT into the circuit to allow the number of NMOS clamp stacks to be reduced.

Abstract: In an ultra high voltage lateral GaN structure having a 2DEG region extending between two terminals, an isolation region is provided between the two terminals to provide for reversible snapback.

Abstract: In a self protected NLDMOS array, a deep implant is included on the drain side of each NLDMOS device to balance ESD current.

Abstract: In an ultra high voltage lateral DMOS-type device (UHV LDMOS device), a central pad that defines the drain region is surrounded by a racetrack-shaped source region with striations of alternating n-type and p-type material radiating outwardly from the pad to the source to provide for an adjustable snapback voltage.

Abstract: Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.

Abstract: In a bipolar device an intrinsic Zener like diode is formed for controlling the triggering voltage and leakage current, the Zener-like diode being formed between the n-collector and the p-base, wherein the collector implant and base diffusion overlap at least partially.