Patents by Inventor Wai-Yan Ho
Wai-Yan Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8694302Abstract: Any primitive cells or blocks can be represented physically by a Barycenter compact model (or Barycenter model), and any black box model can also be physically represented by a Barycenter compact model physically. A hierarchical boundary condition between blocks is formulated by the Barycenter compact model. Hierarchical boundary condition problems between blocks can be limited within two levels only if using the Barycenter compact model.Type: GrantFiled: July 7, 2011Date of Patent: April 8, 2014Assignee: Worldwide Pro Ltd.Inventor: William Wai Yan Ho
-
Patent number: 8667455Abstract: A system or technique provides for a hierarchical visual-based analysis of electrical integrated circuit system simulation results. A 3D visualization may be used to identify and conduct an analysis of the integrated circuit. An analysis is done on a specific feature of the integrated circuit that is visible in the 3D visualization. The specific feature may be one that is obscured by other layers of the integrated circuit visualization.Type: GrantFiled: June 13, 2011Date of Patent: March 4, 2014Assignee: Worldwide Pro Ltd.Inventor: William Wai Yan Ho
-
Patent number: 8554532Abstract: A circuit is simulated by using system or network tearing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, finds a tree, and partitions the tree into two or more subtrees. The technique identifies global links and local links in the graph. Each subtree may be solved individually using distributed, parallel computing. Using the results for the subtrees, the technique obtains a real solution, branch voltages and currents, for the circuit.Type: GrantFiled: February 3, 2012Date of Patent: October 8, 2013Assignee: WorldWide Pro Ltd.Inventor: William Wai Yan Ho
-
Patent number: 8468482Abstract: A technique models and simulates the impact of imperfectly patterned via arrays on integrated circuits through the use of hierarchical models and a hierarchical circuit simulator. Through the hierarchical modeling and simulation approach discussed here, far more accurate electrical simulation and verification of networks is enabled for; performance, yield, and reliability. The approach further enables simulation of the effects of via process variations on large-scale circuit response. In an implementation, each via in a layout or in a via array is modeled as having an independent size from other vias based upon calibrated process simulation. The electrical characteristics of independent vias and via arrays are modeled and compiled into a reusable hierarchical distributed resistance via model. Hierarchical simulation is performed using these hierarchical distributed via models and enables more accurate results than traditional approaches.Type: GrantFiled: March 14, 2011Date of Patent: June 18, 2013Assignee: Worldwide Pro Ltd.Inventors: Robert C. Pack, William Wai Yan Ho
-
Patent number: 8453102Abstract: Technique assesses the impact of physical circuit variations, specification parameter variation, or process variations on clock, signal, and power network performance and through a hierarchical modeling and hierarchical Monte Carlo simulation method.Type: GrantFiled: March 16, 2011Date of Patent: May 28, 2013Assignee: Worldwide Pro Ltd.Inventors: Robert C. Pack, William Wai Yan Ho
-
Patent number: 8396696Abstract: A circuit is simulated by using distributed computing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, finds a tree, and partitions the tree into two or more subtrees. The technique identifies global links and local links in the graph. Each subtree may be solved individually using distributed, parallel computing. Using the results for the subtrees, the technique obtains a real solution, branch voltages and currents, for the circuit.Type: GrantFiled: October 29, 2010Date of Patent: March 12, 2013Assignee: Worldwide Pro Ltd.Inventor: William Wai Yan Ho
-
Patent number: 8166425Abstract: A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws (KVL), and power conservation for the original circuit. A reporting tool shows the validation results and may be customized by the user. The tool can show in the original circuitry where the estimated results may be inaccurate.Type: GrantFiled: September 26, 2008Date of Patent: April 24, 2012Assignee: Worldwide Pro Ltd.Inventor: William Wai Yan Ho
-
Patent number: 8112264Abstract: A circuit is simulated by using system or network tearing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, finds a tree, and partitions the tree into two or more subtrees. The technique identifies global links and local links in the graph. Each subtree may be solved individually using distributed, parallel computing. Using the results for the subtrees, the technique obtains a real solution, branch voltages and currents, for the circuit.Type: GrantFiled: May 31, 2006Date of Patent: February 7, 2012Assignee: Worldwide Pro Ltd.Inventor: William Wai Yan Ho
-
Patent number: 7827016Abstract: A circuit is simulated by using distributed computing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, finds a tree, and partitions the tree into two or more subtrees. The technique identifies global links and local links in the graph. Each subtree may be solved individually using distributed, parallel computing. Using the results for the subtrees, the technique obtains a real solution, branch voltages and currents, for the circuit.Type: GrantFiled: May 31, 2006Date of Patent: November 2, 2010Inventor: William Wai Yan Ho
-
Patent number: 7461360Abstract: A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws (KVL), and power conservation for the original circuit. A reporting tool shows the validation results and may be customized by the user. The tool can show in the original circuitry where the estimated results may be inaccurate.Type: GrantFiled: April 11, 2006Date of Patent: December 2, 2008Inventor: William Wai Yan Ho
-
Patent number: 6438729Abstract: A layout parasitics extraction system uses a connectivity-based approach to permit net-by-net extraction of layout parasitics. The system creates a connectivity-based database (1104), where geometries of a layout are organized by nets of the circuit schematic. The system allows net-by-net extraction (1124) of layout parasitics using a connectivity-based database. A user can select a net or nets for extraction. The system creates a database containing nets and their extracted layout parasitics (1132). The system can generate a netlist format file from this database to provide for back annotation of layout parasitics into a circuit schematic for further circuit analysis.Type: GrantFiled: May 20, 1999Date of Patent: August 20, 2002Assignee: Synopsys, Inc.Inventor: William Wai Yan Ho
-
Patent number: 6421814Abstract: A layout parasitic extraction system is disclosed. The present invention is a connectivity-based approach for extracting layout parasitics. The present invention creates a connectivity-based database, where geometries of a layout are organized by net. The present invention allows net-by-net extraction of layout parasitics using a connectivity-based database. Furthermore, a user can select a net or nets for extraction. The present invention outputs a database containing nets and their extracted layout parasitics. The present invention can create a netlist format file from a database containing nets and their extracted parasitics to allow back annotation of layout parasitics into a circuit schematic or for use for other software (possibly from a third-party).Type: GrantFiled: June 30, 2000Date of Patent: July 16, 2002Assignee: Synopsys, Inc.Inventor: William Wai Yan Ho
-
Patent number: 6378110Abstract: A computer implemented method for verifying a physical layout of an integrated circuit design for a semiconductor chip. The physical layout is specified in terms of a plurality of layers used to fabricate the chip. Initially, a pre-defined set of rules are stored in memory. These rules are used to specify certain dimensions for properly laying out the physical design of the IC. For each rule, one or more layers applicable to that rule is specified. Instead of reading a rule and then applying that rule to the relevant portions of the physical layout, the present invention reads one or more layers pertaining to the physical layout and then determines all rules applicable to those layers. The layers are then verified against the appropriate rules. Any error conditions are stored for subsequent display to the designer or engineer. By performing a layer based rule checking scheme, the number of read operations required, which reduces the time it takes to perform the verification process.Type: GrantFiled: March 31, 1998Date of Patent: April 23, 2002Assignee: Synopsys, Inc.Inventor: William Wai-Yan Ho
-
Patent number: 6128768Abstract: A layout parasitic extraction system is disclosed. The present invention is a connectivity-based approach for extracting layout parasitics. The present invention creates a connectivity-based database, where geometries of a layout are organized by net. The present invention allows net-by-net extraction of layout parasitics using a connectivity-based database. Furthermore, a user can select a net or nets for extraction. The present invention outputs a database containing nets and their extracted layout parasitics. The present invention can create a netlist format file from a database containing nets and their extracted parasitics to allow back annotation of layout parasitics into a circuit schematic or for use for other software (possibly from a third-party).Type: GrantFiled: July 16, 1997Date of Patent: October 3, 2000Assignee: Synopsys, Inc.Inventor: William Wai Yan Ho
-
Layout overlap detection with selective flattening in computer implemented integrated circuit design
Patent number: 6011911Abstract: The present invention relates to a method for efficiently performing hierarchical design rules checks (DRC) and layout versus schematic comparison (LVS) on layout areas of an integrated circuit where cells overlap or where a cell and local geometry overlap. With the present invention, a hierarchical tree describes the integrated circuit's layout data including cells having parent-child relationships and including local geometry. The present invention performs efficient layout verification by performing LVS and DRC checking on the new portions of an integrated circuit design and layout areas containing overlapping cells. When instances of cells overlap, the present invention determines the overlap area using predefined data structures that divide each cell into an array of spatial bins. Each bin of a parent is examined to determine if two or more cell instances reside therein or if a cell instance and local geometry reside therein.Type: GrantFiled: September 30, 1997Date of Patent: January 4, 2000Assignee: Synopsys, Inc.Inventors: Wai-Yan Ho, Hongbo Tang -
Patent number: 6009251Abstract: A method and system for performing layout verification on an integrated circuit (IC) design using reusable subdesigns. Many custom designed integrated circuits are designed and fabricated using a number of computer implemented automatic design processes. Within these processes, a high level design language (e.g., HDL or VHDL) description of the integrated circuit can be translated by a computer system into a netlist of technology specific gates and interconnections there between. The cells of the netlist are then placed spatially in an integrated circuit layout and the connections between the cells are routed using computerized place and route processes. Circuit designers next run layout verification tests on the layout to verify that the geometry and connectivity data of the design meets specific design rules and matches logically with the schematic representation.Type: GrantFiled: September 30, 1997Date of Patent: December 28, 1999Assignee: Synopsys, Inc.Inventors: Wai-Yan Ho, Hongbo Tang
-
Patent number: 6009250Abstract: The present invention relates to a method for efficiently performing hierarchical design rules checks (DRC) and layout versus schematic comparison (LVS) on layout areas of an integrated circuit where cells overlap or where a cell and local geometry overlap. With the present invention, a hierarchical tree describes the integrated circuit's layout data including cells having parent-child relationships and including local geometry. The present invention performs efficient layout verification by performing LVS and DRC checking on the new portions of an integrated circuit design and layout areas containing overlapping cells. When instances of cells overlap, the present invention determines the overlap area using predefined data structures that divide each cell into an array of spatial bins. Each bin of a parent is examined to determine if two or more cell instances reside therein or if a cell instance and local geometry reside therein.Type: GrantFiled: September 30, 1997Date of Patent: December 28, 1999Assignee: Synopsys, Inc.Inventors: Wai-Yan Ho, Hongbo Tang
-
Patent number: 5999726Abstract: A layout parasitics extraction system. The layout parasitics extraction system is a connectivity-based approach for extracting layout parasitics. The system creates a connectivity-based database (1104), where geometries of a layout are organized by nets of the circuit schematic. The system allows net-by-net extraction (1124) of layout parasitics using a connectivity-based database. A user can select a net or nets for extraction. The system creates a database containing nets and their extracted layout parasitics (1132). The system can generate a netlist format file from this database to provide for back annotation of layout parasitics into a circuit schematic for further circuit analysis.Type: GrantFiled: January 23, 1998Date of Patent: December 7, 1999Assignee: Synopsys, Inc.Inventor: William Wai Yan Ho
-
Patent number: 5903469Abstract: A method of extracting layout parasitics for nets of an integrated circuit. The method creates a connectivity-based database (1104), where geometries of a layout are organized by nets of the circuit schematic. The method permits net-by-net extraction (1124) of layout parasitics using a connectivity-based database. A user can select a net or nets for extraction. A net is decomposed into polygon subsections, and parasitics are determined for these subsections. Layout parasitics for some of the decomposed geometries may be found in a predefined geometry library. A database is created containing nets and their extracted layout parasitics (1132). A netlist format file may be generated from this database of extracted parasitics to provide for back annotation of layout parasitics into a circuit schematic for further circuit analysis.Type: GrantFiled: June 6, 1995Date of Patent: May 11, 1999Assignee: Synopsys, Inc.Inventor: William Wai Yan Ho
-
Patent number: 5828580Abstract: A layout parasitic extraction system. The present invention is a connectivity-based approach for extracting layout parasitics. The present invention creates a connectivity-based database, where geometries of a layout are organized by net. The present invention allows net-by-net extraction of layout parasitics using a connectivity-based database. Furthermore, a user can select a net or nets for extraction. The present invention outputs a database containing nets and their extracted layout parasitics. The present invention can create a netlist format file from a database containing nets and their extracted parasitics to allow back annotation of layout parasitics into a circuit schematic or for use for other software (possibly from a third-party).Type: GrantFiled: November 8, 1994Date of Patent: October 27, 1998Assignee: EPIC Design Technology, Inc.Inventor: William Wai Yan Ho