Patents by Inventor Walid M. Hafez
Walid M. Hafez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145477Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ
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Patent number: 11967615Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.Type: GrantFiled: December 23, 2015Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Hsu-Yu Chang, Neville L. Dias, Walid M. Hafez, Chia-Hong Jan, Roman W. Olac-Vaw, Chen-Guan Lee
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Publication number: 20240113128Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.Type: ApplicationFiled: December 13, 2023Publication date: April 4, 2024Inventors: Walid M. HAFEZ, Jeng-Ya D. YEH, Curtis TSAI, Joodong PARK, Chia-Hong JAN, Gopinath BHIMARASETTI
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Patent number: 11935892Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.Type: GrantFiled: July 11, 2022Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Sairam Subramanian, Walid M. Hafez
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Publication number: 20240088253Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Inventors: Tanuj TRIVEDI, Rahul RAMASWAMY, Jeong Dong KIM, Babak FALLAHAZAD, Hsu-Yu CHANG, Ting CHANG, Nidhi NIDHI, Walid M. HAFEZ
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Publication number: 20240038592Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.Type: ApplicationFiled: October 11, 2023Publication date: February 1, 2024Inventors: Roman W. OLAC-VAW, Walid M. HAFEZ, Chia-Hong JAN, Pei-Chi LIU
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Patent number: 11881486Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.Type: GrantFiled: February 17, 2023Date of Patent: January 23, 2024Assignee: Intel CorporationInventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
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Patent number: 11881511Abstract: A transistor is disclosed. The transistor includes a substrate, a superlattice structure that includes a plurality of heterojunction channels, and a gate that extends to one of the plurality of heterojunction channels. The transistor also includes a source adjacent a first side of the superlattice structure and a drain adjacent a second side of the superlattice structure.Type: GrantFiled: December 19, 2018Date of Patent: January 23, 2024Assignee: Intel CorporationInventors: Nidhi Nidhi, Rahul Ramaswamy, Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Johann C. Rode, Paul B. Fischer, Walid M. Hafez
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Patent number: 11876121Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.Type: GrantFiled: July 22, 2022Date of Patent: January 16, 2024Assignee: Intel CorporationInventors: Sairam Subramanian, Walid M. Hafez
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Patent number: 11862703Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.Type: GrantFiled: July 21, 2022Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Babak Fallahazad, Hsu-Yu Chang, Ting Chang, Nidhi Nidhi, Walid M. Hafez
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Publication number: 20230420501Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Inventors: Rahul RAMASWAMY, Walid M. HAFEZ, Tanuj TRIVEDI, Jeong Dong KIM, Ting CHANG, Babak FALLAHAZAD, Hsu-Yu CHANG, Nidhi NIDHI
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Patent number: 11848362Abstract: Disclosed herein are IC structures, packages, and devices that include transistors, e.g., III-N transistors, having a source region, a drain region (together referred to as “source/drain” (S/D) regions), and a gate stack. In one aspect, a contact to at least one of the S/D regions of a transistor may have a width that is smaller than a width of the S/D region. In another aspect, a contact to a gate electrode material of the gate stack of a transistor may have a width that is smaller than a width of the gate electrode material. Reducing the width of contacts to S/D regions or gate electrode materials of a transistor may reduce the overlap area between various pairs of these contacts, which may, in turn, allow reducing the off-state capacitance of the transistor. Reducing the off-state capacitance of III-N transistors may advantageously allow increasing their switching frequency.Type: GrantFiled: April 18, 2019Date of Patent: December 19, 2023Assignee: Intel CorporationInventors: Rahul Ramaswamy, Nidhi Nidhi, Walid M. Hafez, Johann Christian Rode, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Patent number: 11824002Abstract: An integrated circuit structure comprises a base and a plurality of metal levels over the base. A first metal level includes a first dielectric material. The first metal level further includes a first plurality of interconnect lines in the first dielectric material, wherein the first plurality of interconnect lines in the first metal level have variable widths from relatively narrow to relatively wide, and wherein the first plurality of interconnect lines have variable heights based on the variable widths, such that a relatively wide one of the first plurality of interconnect lines has a taller height from the substrate than a relatively narrow one of the first plurality of interconnect lines, and a shorter distance to a top of the first metal level.Type: GrantFiled: June 28, 2019Date of Patent: November 21, 2023Assignee: Intel CorporationInventors: En-Shao Liu, Joodong Park, Chen-Guan Lee, Walid M. Hafez, Chia-Hong Jan, Jiansheng Xu
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Patent number: 11823954Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.Type: GrantFiled: April 13, 2022Date of Patent: November 21, 2023Assignee: Intel CorporationInventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Pei-Chi Liu
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Patent number: 11791380Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.Type: GrantFiled: December 13, 2019Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Rahul Ramaswamy, Walid M. Hafez, Tanuj Trivedi, Jeong Dong Kim, Ting Chang, Babak Fallahazad, Hsu-Yu Chang, Nidhi Nidhi
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Patent number: 11791257Abstract: Integrated circuit structures including device terminal interconnect pillar structures, and fabrication techniques to form such structures. Following embodiments herein, a small transistor terminal interconnect footprint may be achieved by patterning recesses in a gate interconnect material and/or a source or drain interconnect material. A dielectric deposited over the gate interconnect material and/or source or drain interconnect material may be planarized to expose portions of the gate interconnect material and/or drain interconnect material that were protected from the recess patterning. An upper level interconnect structure, such as a conductive line or via, may contact the exposed portion of the gate and/or source or drain interconnect material.Type: GrantFiled: December 27, 2021Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Sairam Subramanian, Walid M. Hafez
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Publication number: 20230317594Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a substrate and a transistor over the substrate. In an embodiment, the transistor comprises a source, a gate, and a drain. In an embodiment, the semiconductor device further comprises a first metal layer above the transistor, where the first metal layer comprises, a source metal coupled to the source, a drain metal coupled to the drain, and a gate metal coupled to the gate. In an embodiment, the source metal, the drain metal, and the gate metal are parallel conductive lines. In an embodiment, a backside via passes through the substrate, and a contact metal in the first metal layer is coupled to the backside via. In an embodiment, the contact metal is oriented orthogonal to the source metal.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Tao CHU, Minwoo JANG, Aurelia WANG, Conor P. PULS, Lin HU, Jaladhi MEHTA, Brian GREENE, Chung-Hsun LIN, Walid M. HAFEZ, Paul PACKAN
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Publication number: 20230299165Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition wide cut gates with non-merged spacers are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is along an end of the first gate stack in the gap. A second dielectric gate spacer is along an end of the second gate stack in the gap. A dielectric liner is in lateral contact with and completely surrounded by the first dielectric gate spacer and the second dielectric gate spacer.Type: ApplicationFiled: March 15, 2022Publication date: September 21, 2023Inventors: Leonard P. GULER, Sairam SUBRAMANIAN, Walid M. HAFEZ, Charles H. WALLACE
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Publication number: 20230299087Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.Type: ApplicationFiled: April 28, 2023Publication date: September 21, 2023Inventors: Curtis TSAI, Chia-Hong JAN, Jeng-Ya David YEH, Joodong PARK, Walid M. HAFEZ
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Patent number: 11764260Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.Type: GrantFiled: October 4, 2021Date of Patent: September 19, 2023Assignee: Tahoe Research, Ltd.Inventors: Walid M. Hafez, Chia-Hong Jan