Patents by Inventor Walid M. Hafez
Walid M. Hafez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11588037Abstract: Disclosed herein are IC structures, packages, and devices that include planar III-N transistors with wrap-around gates and/or one or more wrap-around source/drain (S/D) contacts. An example IC structure includes a support structure (e.g., a substrate) and a planar III-N transistor. The transistor includes a channel stack of a III-N semiconductor material and a polarization material, provided over the support structure, a pair of S/D regions provided in the channel stack, and a gate stack of a gate dielectric material and a gate electrode material provided over a portion of the channel stack between the S/D regions, where the gate stack at least partially wraps around an upper portion of the channel stack.Type: GrantFiled: March 1, 2019Date of Patent: February 21, 2023Assignee: Intel CorporationInventors: Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Johann Christian Rode, Paul B. Fischer, Walid M. Hafez
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Patent number: 11581313Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor regrowth. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by depositing a III-N material, forming an opening in the III-N material, and epitaxially growing within the opening a semiconductor material other than the III-N material. Since the III-N material may serve as a foundation for forming III-N transistors, while the non-III-N material may serve as a foundation for forming non-III-N transistors, such an approach advantageously enables implementation of both types of transistors on a single support structure. Proposed integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.Type: GrantFiled: February 22, 2019Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Sansaptak Dasgupta, Johann Christian Rode, Han Wui Then, Marko Radosavljevic, Paul B. Fischer, Nidhi Nidhi, Rahul Ramaswamy, Sandrine Charue-Bakker, Walid M. Hafez
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Patent number: 11581404Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.Type: GrantFiled: May 5, 2021Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Tanuj Trivedi, Jeong Dong Kim, Walid M. Hafez, Hsu-Yu Chang, Rahul Ramaswamy, Ting Chang, Babak Fallahazad
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Patent number: 11563000Abstract: Gate endcap architectures having relatively short vertical stack, and methods of fabricating gate endcap architectures having relatively short vertical stack, are described. In an example, an integrated circuit structure includes a first semiconductor fin along a first direction. A second semiconductor fin is along the first direction. A trench isolation material is between the first semiconductor fin and the second semiconductor fin. The trench isolation material has an uppermost surface below a top of the first and second semiconductor fins. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin and is along the first direction. The gate endcap isolation structure is on the uppermost surface of the trench isolation material.Type: GrantFiled: March 25, 2020Date of Patent: January 24, 2023Assignee: Intel CorporationInventors: Sairam Subramanian, Walid M. Hafez, Hsu-Yu Chang, Chia-Hong Jan
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Patent number: 11538804Abstract: Disclosed herein are integrated circuit (IC) structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. One example IC structure includes an III-N transistor in a first layer over a support structure (e.g., a substrate) and a TFT in a second layer over the support structure, where the first layer is between the support structure and the second layer. Another example IC structure includes a III-N semiconductor material and a TFT, where at least a portion of a channel material of the TFT is over at least a portion of the III-N semiconductor material.Type: GrantFiled: January 9, 2019Date of Patent: December 27, 2022Assignee: Intel CorporationInventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Walid M. Hafez
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Publication number: 20220399445Abstract: Conductive via bars self-aligned to gate ends are described. In an example, an integrated circuit structure includes a plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A conductive via bar is along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar.Type: ApplicationFiled: June 14, 2021Publication date: December 15, 2022Inventors: Leonard P. GULER, Tahir GHANI, Charles H. WALLACE, Conor P. PULS, Walid M. HAFEZ, Sairam SUBRAMANIAN, Justin S. SANDFORD, Saurabh MORARKA, Sean PURSEL, Mohammad HASAN
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Patent number: 11527532Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor-based cascode arrangements that may simultaneously realize enhancement mode transistor operation and high voltage capability. In one aspect, an IC structure includes a source region, a drain region, an enhancement mode III-N transistor, and a depletion mode III-N transistor, where each of the transistors includes a first and a second source or drain (S/D) terminals. The transistors are arranged in a cascode arrangement in that the first S/D terminal of the enhancement mode III-N transistor is coupled to the source region, the second S/D terminal of the enhancement mode III-N transistor is coupled to the first S/D terminal of the depletion mode III-N transistor, and the second S/D terminal of the depletion mode III-N transistor is coupled to the drain region.Type: GrantFiled: May 22, 2019Date of Patent: December 13, 2022Assignee: Intel CorporationInventors: Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
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Patent number: 11502191Abstract: Disclosed herein are IC structures that implement field plates for III-N transistors in a form of electrically conductive structures provided in a III-N semiconductor material below the polarization layer (i.e., at the “backside” of an IC structure). In some embodiments, such a field plate may be implemented as a through-silicon via (TSV) extending from the back/bottom face of the substrate towards the III-N semiconductor material. Implementing field plates at the backside may provide a viable approach to changing the distribution of electric field at a transistor drain and increasing the breakdown voltage of an III-N transistor without incurring the large parasitic capacitances associated with the use of metal field plates provided above the polarization material. In addition, backside field plates may serve as a back barrier for advantageously reducing drain-induced barrier lowering.Type: GrantFiled: February 14, 2019Date of Patent: November 15, 2022Assignee: Intel CorporationInventors: Johann Christian Rode, Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Walid M. Hafez
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Publication number: 20220359705Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.Type: ApplicationFiled: July 22, 2022Publication date: November 10, 2022Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ
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Publication number: 20220359697Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Inventors: Tanuj TRIVEDI, Rahul RAMASWAMY, Jeong Dong KIM, Babak FALLAHAZAD, Hsu-Yu CHANG, Ting CHANG, Nidhi NIDHI, Walid M. HAFEZ
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Publication number: 20220352165Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.Type: ApplicationFiled: July 11, 2022Publication date: November 3, 2022Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ
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Patent number: 11450617Abstract: IC structures that include transmission line structures to be integrated with III-N devices are disclosed. An example transmission line structure includes a transmission line of an electrically conductive material provided above a stack of a III-N semiconductor material and a polarization material. The transmission line structure further includes means for reducing electromagnetic coupling between the line and charge carriers present below the interface of the polarization material and the III-N semiconductor material. In some embodiments, said means include a shield material of a metal or a doped semiconductor provided over portions of the polarization material that are under the transmission line. In other embodiments, said means include dopant atoms implanted into the portions of the polarization material that are under the transmission line, and into at least an upper portion of the III-N semiconductor material under such portions of the polarization material.Type: GrantFiled: March 15, 2019Date of Patent: September 20, 2022Assignee: Intel CorporationInventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Nidhi Nidhi, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
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Patent number: 11444171Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.Type: GrantFiled: March 6, 2019Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Sairam Subramanian, Walid M. Hafez
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Patent number: 11437483Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.Type: GrantFiled: March 5, 2020Date of Patent: September 6, 2022Assignee: Intel CorporationInventors: Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Babak Fallahazad, Hsu-Yu Chang, Ting Chang, Nidhi Nidhi, Walid M. Hafez
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Patent number: 11424245Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.Type: GrantFiled: March 6, 2019Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Sairam Subramanian, Walid M. Hafez
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Publication number: 20220238383Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.Type: ApplicationFiled: April 13, 2022Publication date: July 28, 2022Inventors: Roman W. OLAC-VAW, Walid M. HAFEZ, Chia-Hong JAN, Pei-Chi LIU
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Patent number: 11387328Abstract: Group-III nitride (III-N) tunnel devices with a device structure including multiple quantum wells. A bias voltage applied across first device terminals may align the band structure to permit carrier tunneling between a first carrier gas residing in a first of the wells to a second carrier gas residing in a second of the wells. A III-N tunnel device may be operable as a diode, or further include a gate electrode. The III-N tunnel device may display a non-linear current-voltage response with negative differential resistance, and be employed as a frequency mixer operable in the GHz and THz bands. In some examples, a GHz-THz input RF signal and local oscillator signal are coupled into a gate electrode of a III-N tunnel device biased within a non-linear regime to generate an output RF signal indicative of a frequency difference between the RF signal and a local oscillator signal.Type: GrantFiled: September 27, 2018Date of Patent: July 12, 2022Assignee: Intel CorporationInventors: Rahul Ramaswamy, Walid M. Hafez, Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then, Nidhi Nidhi
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Publication number: 20220173105Abstract: Metal fuses and self-aligned gate edge (SAGE) architectures having metal fuses are described. In an example, an integrated circuit structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal fuse is on the gate edge isolation structure.Type: ApplicationFiled: February 21, 2022Publication date: June 2, 2022Inventors: Rohan K. BAMBERY, Walid M. HAFEZ, Mong-Kai WU
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Patent number: 11335601Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.Type: GrantFiled: December 4, 2020Date of Patent: May 17, 2022Assignee: Intel CorporationInventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Pei-Chi Liu
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Patent number: 11329138Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.Type: GrantFiled: April 2, 2018Date of Patent: May 10, 2022Assignee: Intel CorporationInventors: Sairam Subramanian, Christopher Kenyon, Sridhar Govindaraju, Chia-Hong Jan, Mark Liu, Szuya S. Liao, Walid M. Hafez