Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. EM rule is kept on the metal segment when a single via is formed over and in contact with the metal segment in the layout. The EM rule is relaxed on the metal segment when two first vias are formed over and in contact with the metal segment in the layout. The two first vias have the same current direction.

Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitances, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.

Abstract: In a method, based on an operating condition of a region of an integrated circuit (IC), a first relationship between a temperature and heating power of the region is determined. Based on a cooling capacity of the region, a second relationship between the temperature and cooling power of the region is determined. Based on the first relationship and the second relationship, it is determined whether the region is thermally stable. In response to a determination that the region is thermally unstable, at least one of a structure or the operating condition of the region is changed. At least one of the determination of the first relationship, the determination of the second relationship, the determination of thermally stability of the region, or the change of at least one of the structure or the operating condition of the region is executed by a processor.

Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to the current simulation result of the IC. It is determined whether to relax the EM rule on the metal segment according to the number of vias over the metal segment in the layout. The vias are in contact with the metal segment.

Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.

Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to the current simulation result of the IC. It is determined whether to relax the EM rule on the metal segment according to the number of vias over the metal segment in the layout. The vias are in contact with the metal segment.

Abstract: In a method, based on an operating condition of a region of an integrated circuit (IC), a first relationship between a temperature and heating power of the region is determined. Based on a cooling capacity of the region, a second relationship between the temperature and cooling power of the region is determined. Based on the first relationship and the second relationship, it is determined whether the region is thermally stable. In response to a determination that the region is thermally unstable, at least one of a structure or the operating condition of the region is changed. At least one of the determination of the first relationship, the determination of the second relationship, the determination of thermally stability of the region, or the change of at least one of the structure or the operating condition of the region is executed by a processor.

Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.

Abstract: A method includes receiving an input that is in an electronic file format and that includes information associated with an integrated circuit (IC) layout, selecting a non EM rule compliant metal line of the IC layout that is in violation of an EM rule from the input, obtaining a current of the non EM rule compliant metal line from the input, comparing the current with a threshold current, and determining whether the EM rule violation is negligible based on the result of comparison. As such, a semiconductor device may be fabricated from the IC layout when it is determined that the EM rule violation is negligible.

Abstract: An integrated fan-out package and a layout method thereof are provided. One integrated fan-out package includes a die and a fan-out substrate. The die has an interconnect structure therein. The fan-out substrate has a redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof. The first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a redistribution layer of the redistribution layer structure, and an aspect ratio of the first conductive bumps ranges from about 1/3 to 1/10.

Abstract: A method includes receiving an input that is in an electronic file format and that includes information associated with an integrated circuit (IC) layout, selecting a non EM rule compliant metal line of the IC layout that is in violation of an EM rule from the input, obtaining a current of the non EM rule compliant metal line from the input, comparing the current with a threshold current, and determining whether the EM rule violation is negligible based on the result of comparison. As such, a semiconductor device may be fabricated from the IC layout when it is determined that the EM rule violation is negligible.

Abstract: An integrated fan-out package and a layout method thereof are provided. One integrated fan-out package includes a die and a fan-out substrate. The die has an interconnect structure therein. The fan-out substrate has a redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof. The first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a redistribution layer of the redistribution layer structure, and an aspect ratio of the first conductive bumps ranges from about 1/3 to 1/10.

Abstract: A pixel structure and a method of manufacturing a pixel structure are provided. The pixel structure includes an active device, a gate insulation layer, a dielectric insulation layer, a capacitance electrode, a protection layer and a pixel electrode. The active device includes a gate, a semiconductor channel layer, a source and a drain. The dielectric insulation layer covers the semiconductor channel layer. A dielectric index of the dielectric insulation layer is greater than a dielectric index of the gate insulation layer. The capacitance electrode is overlapped with the drain. The capacitance electrode, the drain and the dielectric insulation layer between the two constitute a storage capacitor structure. The protection layer is disposed on the dielectric insulation layer and the capacitance electrode is located between the protection layer and the dielectric insulation layer. The pixel electrode is disposed on the protection layer and connected to the drain of the active device.

Abstract: An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit.

Abstract: An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit.

Abstract: A method of making a semiconductor device includes determining, by a processor, a first pattern density of a first region, determining a second pattern density of a second region, determining a pattern density gradient from the first region to the second region, determining whether the pattern density gradient exceeds a pattern density gradient threshold and performing a placement or a routing of the semiconductor device if the pattern density gradient is less than or equal to the pattern density gradient threshold.

Abstract: A pixel structure and a method of manufacturing a pixel structure are provided. The pixel structure includes an active device, a gate insulation layer, a dielectric insulation layer, a capacitance electrode, a protection layer and a pixel electrode. The active device includes a gate, a semiconductor channel layer, a source and a drain. The dielectric insulation layer covers the semiconductor channel layer. A dielectric index of the dielectric insulation layer is greater than a dielectric index of the gate insulation layer. The capacitance electrode is overlapped with the drain. The capacitance electrode, the drain and the dielectric insulation layer between the two constitute a storage capacitor structure. The protection layer is disposed on the dielectric insulation layer and the capacitance electrode is located between the protection layer and the dielectric insulation layer. The pixel electrode is disposed on the protection layer and connected to the drain of the active device.

Abstract: A pixel structure and a method of manufacturing a pixel structure are provided. The pixel structure includes an active device, a gate insulation layer, a dielectric insulation layer, a capacitance electrode, a protection layer and a pixel electrode. The active device includes a gate, a semiconductor channel layer, a source and a drain. The dielectric insulation layer covers the semiconductor channel layer. A dielectric index of the dielectric insulation layer is greater than a dielectric index of the gate insulation layer. The capacitance electrode is overlapped with the drain. The capacitance electrode, the drain and the dielectric insulation layer between the two constitute a storage capacitor structure. The protection layer is disposed on the dielectric insulation layer and the capacitance electrode is located between the protection layer and the dielectric insulation layer. The pixel electrode is disposed on the protection layer and connected to the drain of the active device.

Abstract: In some embodiments, in a method, a layout of a circuit is received. A netlist with indicated pattern density (PD)-dependent mismatch elements associated with different PDs, respectively, is generated using the layout. A simulation on the netlist is performed such that when the PD-dependent mismatch elements are modeled in the simulation, corresponding model parameters of the PD-dependent mismatch elements are generated using variation distributions with different spreads.

Abstract: In some embodiments, in a method, a layout of a circuit is received. A netlist with indicated pattern density (PD)-dependent mismatch elements associated with different PDs, respectively, is generated using the layout. A simulation on the netlist is performed such that when the PD-dependent mismatch elements are modeled in the simulation, corresponding model parameters of the PD-dependent mismatch elements are generated using variation distributions with different spreads.