Abstract: Shielded semiconductor devices and methods for fabricating shielded semiconductor devices are provided. An exemplary magnetically shielded semiconductor device includes a substrate having a top surface and a bottom surface. An electromagnetic-field-susceptible semiconductor component is located on and/or in the substrate. The magnetically shielded semiconductor device includes a top magnetic shield located over the top surface of the substrate. Further, the magnetically shielded semiconductor device includes a bottom magnetic shield located under the bottom surface of the substrate. Also, the magnetically shielded semiconductor device includes a sidewall magnetic shield located between the top magnetic shield and the bottom magnetic shield.

Abstract: Methods of forming planar RRAM and vertical RRAM with tip electrodes and the resulting devices are provided. Embodiments include forming a first metal oxide layer on a first dielectric layer; forming and patterning a mask layer over the first metal oxide layer; etching the first metal oxide through the mask layer to form openings for a first and second metal electrodes; removing the mask layer; forming the first and second metal electrodes in the openings; and forming a second metal oxide layer over the first and second metal electrodes, wherein the first and second metal electrodes are v-shaped in top view with tips of the first and second metal electrodes facing each other and a portion of the second metal oxide layer being formed between the tips of the first and second electrodes.

Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.

Abstract: A method for forming a MRAM device free of seal ring peeling defect, and the resulting device, are provided. Embodiments include forming magnetic tunnel junction (MTJ) over a metallization layer in a seal ring region of an MRAM device; forming a metal filled via connecting the MTJ and the metallization layer; forming a tunnel junction via over the MTJ; and forming a top electrode over the tunnel junction via.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate having a buried insulator layer and an active layer overlying the buried insulator layer. A transistor overlies the buried insulator layer, and a memory cell underlies the buried insulator layer. As such, the memory cell and the transistor are on opposite sides of the buried insulator layer.

Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.

Abstract: Methods of forming a pillar contact extension within a memory device using a self-aligned planarization process rather than direct ILD CMP and the resulting devices are provided. Embodiments include forming a photoresist layer over a low-K layer formed over an ILD having a first metal layer in a memory region and in a logic region and pillar-shaped conductors formed atop of the first metal layer only in the memory region; forming a trench through the photoresist layer over each pillar-shaped conductor; extending the trench through the low-K layer to an upper surface of each pillar-shaped conductor; forming a second metal layer over the low-K layer, filling the trench entirely; and planarizing the second metal layer until the second metal layer is removed from over the logic region, a pillar contact extension formed atop of each pillar-shaped conductor.

Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.

Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.

Abstract: Methods of magnetically shielding a perpendicular STT-MRAM structure on all six sides within a flip-chip package and the resulting devices are provided. Embodiments include forming a passivation stack over an upper surface of a wafer and outer portions of an Al pad; forming a polymer layer over the passivation stack; forming a UBM layer over the Al pad, portions of the polymer layer and along sidewalls of the polymer layer; forming a T-shaped Cu pillar over the UBM layer; forming a ?-bump over the T-shaped Cu pillar; dicing the wafer into a plurality of dies; forming an epoxy layer over a bottom surface of each die; forming a magnetic shielding layer over the epoxy layer and along sidewalls of each die, the epoxy layer, the passivation stack and the polymer layer; and connecting the ?-bump to a package substrate with a BGA balls.

Abstract: Methods of magnetically shielding a perpendicular STT-MRAM structure on all six sides within a flip-chip package and the resulting devices are provided. Embodiments include forming a passivation stack over an upper surface of a wafer and outer portions of an Al pad; forming a polymer layer over the passivation stack; forming a UBM layer over the Al pad, portions of the polymer layer and along sidewalls of the polymer layer; forming a T-shaped Cu pillar over the UBM layer; forming a ?-bump over the T-shaped Cu pillar; dicing the wafer into a plurality of dies; forming an epoxy layer over a bottom surface of each die; forming a magnetic shielding layer over the epoxy layer and along sidewalls of each die, the epoxy layer, the passivation stack and the polymer layer; and connecting the ?-bump to a package substrate with a BGA balls.

Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAIVI layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.

Abstract: A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.

Abstract: A scalable method of forming an integrated high-density STT-MRAM with a 3D array of multi-level MTJs and the resulting devices are provided. Embodiments include providing a Si substrate of an X-density STT-MRAM having an array of interconnect stacks; forming a level of a MTJ structure on each of a first interconnect stack and a second interconnect stack, wherein (X?1) defines a number of interconnect stacks between the first and the second interconnect stacks; forming a via on each interconnect stack without a MTJ structure; forming a metal layer on each MTJ structure and via on the level; repeating the forming of the MTJ structure, the via, and the metal layer one interconnect stack laterally shifted until the level of the MTJ structure equals X, only forming the MTJ structure at that level; forming a bit line over the substrate; and connecting the bit line to each MTJ structure.

Abstract: A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.

Abstract: A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.

Abstract: High density resistive memory structures, integrate circuits with high density resistive memory structures, and methods for fabricating high density resistive memory structures are provided. In an embodiment, a high density resistive memory structure includes a semiconductor substrate and a plurality of first electrodes in a first plane in and/or over the semiconductor substrate. Further, the high density resistive memory structure includes a plurality of second electrodes in a second plane in and/or over the semiconductor substrate. The second plane is parallel to the first plane, and each second electrode in the plurality of second electrodes crosses over or under each first electrode in the plurality of first electrodes at a series of cross points. Each second electrode in the plurality of second electrodes is non-linear and the series of cross points formed by each respective second electrode is non-linear.

Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a capacitor, where the capacitor includes a first capacitor plate and a second capacitor plate. The first capacitor plate includes a first memory cell, and the second capacitor plate includes a second memory cell. The capacitor is utilized as a functional capacitor in the integrated circuit.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate having a buried insulator layer and an active layer overlying the buried insulator layer. A transistor overlies the buried insulator layer, and a memory cell underlies the buried insulator layer. As such, the memory cell and the transistor are on opposite sides of the buried insulator layer.