Abstract: This invention comprises various high production methods for simultaneously forming surface metallizations on a plurality of monolithic electronic modules. Each monolithic electronic module may comprise a single semiconductor chip or multiple semiconductor chips. The methods can employ a workpiece which automatically discontinues side surface metallization between different electronic modules in the stack. Multiple workpieces are interleaved within the stack between the electronic modules. Each workpiece may include a transfer layer(s) for permanent bonding to an end surface of an adjacent electronic module in the stack. This transfer layer may comprise an insulation layer, a metallization layer, an active circuit layer, or any combination thereof. End surface metallization can thus be provided contemporaneous with side surface metallization of multiple electronic modules.

Abstract: Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results.

Abstract: Electronic semiconductor structures utilize an electrically programmable spare circuit incorporated with a multichip package. The programmable sparing capability in the multichip package is accomplished either with or without the inclusion of a spare chip(s). With a spare memory circuit, individual failed memory cells in the semiconductor chips of a stack can be functionally replaced by memory cells of the spare memory circuit subsequent to encapsulation and burn-in testing. With use of a spare chip, non-volatile sparing can occur subsequent to encapsulation and burn-in testing without physical rewiring of a wire bond connection. Specific details of alternate electronic semiconductor structures, and fabrication and sparing methods therefore, are set forth.

Abstract: An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit.

Abstract: A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer is insulated from the chip face and from the adjacent chip in the stack by polymer layers having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

Abstract: Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results.