Patents by Inventor Wei-Chen Lin
Wei-Chen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240161787Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.Type: ApplicationFiled: August 10, 2023Publication date: May 16, 2024Inventors: Chien-Chen Lin, Wei Min Chan
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Publication number: 20240154021Abstract: A p-GaN high-electron-mobility transistor (HEMT) includes a buffer layer stacked on a substrate, a channel layer stacked on the buffer layer, a supply layer stacked on the channel layer, a doped layer stacked on the supply layer, and a hydrogen barrier layer covering the supply layer and the doped layer. A source and a drain are electrically connected to the channel layer and the supply layer, respectively. A gate is located on the doped layer. The hydrogen barrier layer is doped with fluorine.Type: ApplicationFiled: December 29, 2022Publication date: May 9, 2024Inventors: TING-CHANG CHANG, Wei-Chen Huang, Shih-Kai Lin, Yong-Ci Zhang, Sheng-Yao Chou, Chung-Wei Wu, Po-Hsun Chen
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Publication number: 20240154314Abstract: An antenna device includes a substrate, two T-shaped radiation portions, two feeding portions and an isolation structure. The substrate has an upper surface, a side surface and a lower surface. Two opposite ends of the side surface are connected to the upper surface and the lower surface, respectively. The two T-shaped radiation portions are located on the upper surface of the substrate. The two feeding portions are connected to the two T-shaped radiation portions, respectively, and the two feeding portions are located on the side surface of the substrate. The isolation structure is located on the upper surface of the substrate, and the isolation structure is disposed between the two T-shaped radiation portions.Type: ApplicationFiled: March 1, 2023Publication date: May 9, 2024Inventors: Hsin-Hung Lin, Yu Shu Tai, WEI-CHEN CHENG
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Publication number: 20240153901Abstract: A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.Type: ApplicationFiled: January 9, 2023Publication date: May 9, 2024Inventors: Yu-Hung Lin, Han-Jong Chia, Wei-Ming Wang, Kuo-Chung Yee, Chen Chen, Shih-Peng Tai
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Publication number: 20240143141Abstract: The present disclosure generally relates to underwater user interfaces.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: Benjamin W. BYLENOK, Alan AN, Richard J. BLANCO, Andrew CHEN, Maxime CHEVRETON, Kyle B. CRUZ, Walton FONG, Ki Myung LEE, Sung Chang LEE, Cheng-I LIN, Kenneth H. MAHAN, Anya PRASITTHIPAYONG, Alyssa RAMDYAL, Eric SHI, Xuefeng WANG, Wei Guang WU
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Publication number: 20240134163Abstract: An image capturing lens assembly includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, and a sixth lens element. The first lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The second and third lens elements have refractive power. The fourth lens element has positive refractive power. The fifth lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof. The sixth lens element with refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The image capturing lens assembly has a total of six lens elements with refractive power.Type: ApplicationFiled: December 28, 2023Publication date: April 25, 2024Applicant: LARGAN PRECISION CO., LTD.Inventors: Cheng-Chen LIN, Wei-Yu CHEN
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Publication number: 20240138138Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Inventors: SHIH-FAN KUAN, WEI-CHEN PAN, YU-TING LIN, HUEI-RU LIN
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Publication number: 20240138139Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.Type: ApplicationFiled: July 17, 2023Publication date: April 25, 2024Inventors: SHIH-FAN KUAN, WEI-CHEN PAN, YU-TING LIN, HUEI-RU LIN
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Patent number: 11956919Abstract: A cold plate is provided and includes: a housing disposed with a chamber; a base combined with the housing to form a working space separated from the chamber but connected with the chamber through an interconnecting structure to allow a working medium to flow within the chamber and the working space; a heat transfer structure disposed on the inner side of the base; and a pump disposed within the working space to drive the working medium in the working space. As such, the cold plate can provide better heat dissipation performance.Type: GrantFiled: December 23, 2020Date of Patent: April 9, 2024Assignee: AURAS TECHNOLOGY CO., LTD.Inventors: Chien-An Chen, Chien-Yu Chen, Tian-Li Ye, Jen-Hao Lin, Wei-Shen Lee
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Patent number: 11942699Abstract: An antenna device includes a first insulation layer, a defected metal layer, a second insulation layer, and a plurality of radiators. The defected metal layer is disposed on the first insulation layer, and the defected metal layer has a plurality of recess features which are arranged with uniform pitches. The second insulation layer is disposed on the first insulation layer and the defected metal layer. The radiators are disposed on the second insulation layer, and each radiator has a feeding portion and a grounding portion.Type: GrantFiled: June 13, 2022Date of Patent: March 26, 2024Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATIONInventors: Hsin-Hung Lin, Wei Chen Cheng
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Publication number: 20240097351Abstract: The present disclosure provides an antenna system, which includes a defected ground structure board and an antenna structure board. The defected ground structure board includes a first insulating plate and a defected ground structure layer, and the defected ground structure layer is disposed on the first insulating plate. The antenna structure board is disposed on the defected ground structure board. The antenna structure board includes at least one antenna body and a second insulating plate, the at least one antenna body is disposed on the second insulating plate, and the second insulating plate is disposed on the defected ground structure layer.Type: ApplicationFiled: December 19, 2022Publication date: March 21, 2024Inventors: Hsin Hung LIN, Yu Shu TAI, Wei Chen CHENG
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Publication number: 20240096830Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.Type: ApplicationFiled: January 9, 2023Publication date: March 21, 2024Inventors: Yu-Yi Huang, Yu-Hung Lin, Wei-Ming Wang, Chen Chen, Shih-Peng Tai, Kuo-Chung Yee
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Patent number: 11930614Abstract: A server includes a casing, a storage device, and a storage device frame assembly. The casing includes a first side plate. The storage device frame assembly includes a support frame and a handle. The support frame accommodates the storage device and is removably mounted on the first side plate. The handle includes a pivotable component and a slidable component. The pivotable component is pivotably disposed on the support frame. The slidable component is slidably disposed on the pivotable component. The slidable component is slidable between a first position and a predetermined position relative to the pivotable component, a longitudinal axis of the slidable component in the first position is non-parallel to the longitudinal axis of the slidable component in the predetermined position.Type: GrantFiled: May 3, 2023Date of Patent: March 12, 2024Assignee: WIWYNN CORPORATIONInventor: Wei Chen Lin
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Publication number: 20240076797Abstract: A susceptor assembly for supporting a crucible during a crystal growth process includes a susceptor base, a tubular sidewall connected to the susceptor base, and a removable sacrifice ring interposed between the susceptor base and the sidewall. Each of the susceptor base and the sidewall is formed of a carbon-containing material. The susceptor base has an annular wall and a shoulder extending radially outward from an outer surface of the annular wall. The sidewall has a first end that receives the annular wall to connect the sidewall to the susceptor base. The sacrifice ring has a first surface that faces the outer surface of the annular wall, a second surface that faces an interior surface of the sidewall, and a ledge extending outward from the second surface that engages the first end of the sidewall.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Inventors: Hong-Huei Huang, Benjamin Michael Meyer, Chun-Sheng Wu, Wei-Chen Chou, Chen-Yi Lin, Feng-Chien Tsai
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Patent number: 11914582Abstract: One or more computing devices, systems, and/or methods for generating a list of suggested queries associated with one or more keywords are provided. For example, one or more keywords may be received via a search interface. A plurality of queries associated with the one or more keywords may be determined based upon the one or more keywords and a historical query database. A plurality of relationship scores associated with the plurality of queries may be generated based upon a plurality of search sessions associated with the historical query database. The historical query database may be analyzed to determine a plurality of click rates associated with the plurality of queries. A list of suggested queries may be generated based upon the plurality of relationship scores and the plurality of click rates.Type: GrantFiled: June 28, 2022Date of Patent: February 27, 2024Assignee: Yahoo Assets LLCInventors: Su-Chen Lin, Jian-Chih Ou, Tzu-Chiang Liou, Wei-Lun Su
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Patent number: 11860612Abstract: An automatic testing method includes obtaining a positioning image, analyzing position of a plurality of slots of the test motherboard in the positioning image to generate route information for insertion and testing of components; wherein photographing test motherboard and obtaining positioning image focused on the test motherboard, controlling the clamping device to insert a plurality of the components into the slots according to the route information, controlling the test motherboard to test the components, determining if there is a faulty component, controlling the clamping device to withdraw and insert the components into other slots according to the route information and controlling the test motherboard to retest the components again if there is no faulty component. An automatic testing device and a non-volatile storage medium performing the above-described method are also disclosed.Type: GrantFiled: April 27, 2022Date of Patent: January 2, 2024Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.Inventors: Wei-Chen Lin, Duo Qiu, Ya-Nan Bian
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Publication number: 20230354549Abstract: A validation method relating to the validation of immersion-cooled servers in an air cooling environment obtains a requirement or purchase order, the order including types of immersion-cooled servers and number required. The method builds a validation environment accordingly, the validation environment includes first fans and air cooling power modules. The air cooling power modules includes a number of power supply units and a number of second fans. The method executes one or more tests in an assembled validation environment. The method further generates a result of test. A demo board and a non-transitory storage medium are also disclosed.Type: ApplicationFiled: November 30, 2022Publication date: November 2, 2023Inventors: LI-QUAN HE, DUO QIU, WEI-CHEN LIN
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Publication number: 20230350386Abstract: A method for managing a management board of an immersion cooling tank detects a signal of each of the first terminals of the management board. The method determines a first number of levels of the detected signals being high and a second number of the levels of the detected signals being low. The method further determines whether the management board is the master management board or is the slave management board according to the first number and the second number. The management board is determined to be the master management board if the levels of all of the detected signals are low. A related management board of an immersion cooling tank and a non-transitory storage medium are also provided.Type: ApplicationFiled: November 30, 2022Publication date: November 2, 2023Inventors: DUO QIU, LI-QUAN HE, WEI-CHEN LIN
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Publication number: 20230315068Abstract: An automatic testing method includes obtaining a positioning image, analyzing position of a plurality of slots of the test motherboard in the positioning image to generate route information for insertion and testing of components; wherein photographing test motherboard and obtaining positioning image focused on the test motherboard, controlling the clamping device to insert a plurality of the components into the slots according to the route information, controlling the test motherboard to test the components, determining if there is a faulty component, controlling the clamping device to withdraw and insert the components into other slots according to the route information and controlling the test motherboard to retest the components again if there is no faulty component. An automatic testing device and a non-volatile storage medium performing the above-described method are also disclosed.Type: ApplicationFiled: April 27, 2022Publication date: October 5, 2023Inventors: Wei-Chen Lin, Duo Qiu, Ya-Nan Bian
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Publication number: 20230269898Abstract: A server includes a casing, a storage device, and a storage device frame assembly. The casing includes a first side plate. The storage device frame assembly includes a support frame and a handle. The support frame accommodates the storage device and is removably mounted on the first side plate. The handle includes a pivotable component and a slidable component. The pivotable component is pivotably disposed on the support frame. The slidable component is slidably disposed on the pivotable component. The slidable component is slidable between a first position and a predetermined position relative to the pivotable component, a longitudinal axis of the slidable component in the first position is non-parallel to the longitudinal axis of the slidable component in the predetermined position.Type: ApplicationFiled: May 3, 2023Publication date: August 24, 2023Inventor: Wei Chen Lin