Abstract: This application discloses electromagnetic energy mitigation assemblies and automotive vehicle components comprising the electromagnetic energy mitigation assemblies. An electromagnetic energy mitigation assembly includes a first electrically conductive layer and a second electrically conductive layer. First and second permalloy layers are along respective first and second opposite sides of the first electrically conductive layer. Third and fourth permalloy layers are along respective third and fourth opposite sides of the second electrically conductive layer. An electromagnetic noise suppression layer is sandwiched between the second and third permalloy layers. An automotive vehicle component includes an electromagnetic energy mitigation assembly configured to be positioned relative to one or more batteries of an automotive vehicle for providing electromagnetic shielding for the one or more batteries. The electromagnetic energy mitigation assembly includes a first electrically conductive layer.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: The present application provides a memory device having a word line with an improved adhesion between a work function member and a conductive layer. The memory device includes a semiconductor substrate defined with an active area and including a recess extending into the semiconductor substrate, and a word line disposed within the recess, wherein the word line includes a first insulating layer disposed within and conformal to the recess, a conductive layer surrounded by the first insulating layer, a conductive member enclosed by the conductive layer, and a second insulating layer disposed over the conductive layer and conformal to the first insulating layer. A method of manufacturing the memory device is also disclosed.

Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

Abstract: An integrated fan-out (InFO) package includes a die, an encapsulant, a redistribution structure, a slot antenna, an insulating layer, a plurality of conductive structures, and an antenna confinement structure. The encapsulant laterally encapsulates the die. The redistribution structure is disposed on the die and the encapsulant. The slot antenna is disposed above the redistribution structure. The insulating layer is sandwiched between the redistribution structure and the slot antenna. The conductive structures and the antenna confinement structure extend from the slot antenna to the redistribution structure.

Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.

Abstract: A display panel includes a first substrate, pixel structures, a first common pad, a second substrate, a second common electrode, a display medium and a conductive particle. The pixel structures are disposed on an active area of the first substrate. The first common pad is disposed on a peripheral area of the first substrate, and is electrically connected to first common electrodes of the pixel structures. The second common electrode is disposed on the second substrate. The conductive particle is disposed on the first common pad, and is electrically connected to the first common pad and the second common electrode. The conductive particle includes a core and a conductive film disposed on a surface of the core, where the conductive film has a main portion and raised portions, and a film thickness of each of the raised portions is greater than a film thickness of the main portion.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and with a top surface of the first through-substrate via; and an interconnect structure including a first dielectric layer and first conductive vias, the first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate, the first conductive vias extending through the first dielectric layer to contact the top surface of the first through-substrate via.

Abstract: A semiconductor device includes a first contact layer, a second contact layer, an active layer, a photonic crystal layer, a passivation layer, a first electrode and a second electrode. The first contact layer has a first surface and a second surface opposite to each other. Microstructures are located on the second surface. The second contact layer is located below the first surface. The active layer is located between the first contact layer and the second contact layer. The photonic crystal layer is located between the active layer and the second contact layer. The passivation layer is located on the second contact layer. The first electrode is located on the passivation layer and is electrically connected the first surface of the first contact layer. The second electrode is located on the passivation layer and is electrically connected to the second contact layer.

Abstract: A memory device includes a multi-layer stack, a channel layer, a memory material layer and at least three conductive pillars. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer and memory material layer penetrate through the plurality of conductive layers and the plurality of dielectric layers. The at least three conductive pillars are surrounded by the channel layer and the memory material layer, wherein the at least three conductive pillars are electrically connected to conductive layers respectively. The at least three conductive pillars includes a first, a second and a third conductive pillars disposed between the first conductive pillar and the second conductive pillar. A third width of the third conductive pillar is smaller than a first width of the first conductive pillar and a second width of the second conductive pillar.

Abstract: A method of using NC-MRA to generate pelvic veins images and measure rate of blood flow includes subjecting a lay patient to undergo magnetic resonance scan in cooperation with an ECG monitor and a respiration monitor; scanning coronary sections and transverse sections of kidney veins, lower cavity veins, common iliac veins, and external iliac veins to generate two-dimensional images wherein the two-dimensional images use balanced turbo field echo wave sequence; scanning coronary sections of common cardinal veins of abdominal cavity to generate three-dimensional images wherein the three-dimensional images use fast spin-echo short tau inversion recovery wave sequence and sample signals when the ECG monitor monitors myocardial contractility; and using quantification phase-contrast analysis to measure blood flowing through the transverse sections of the veins in a two-dimensional scan.

Abstract: In an embodiment, a device includes: a first integrated circuit die comprising a semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first integrated circuit die, a surface of the gap-fill dielectric being substantially coplanar with an inactive surface of the semiconductor substrate and with a surface of the first through-substrate via; a dielectric layer on the surface of the gap-fill dielectric and the inactive surface of the semiconductor substrate; a first bond pad extending through the dielectric layer to contact the surface of the first through-substrate via, a width of the first bond pad being less than a width of the first through-substrate via; and a second integrated circuit die comprising a die connector bonded to the first bond pad.

Abstract: A video codec receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video codec signals or parses a first syntax element for a first coding mode in a particular set of two or more coding modes. Each of coding mode of the particular set of coding modes modifies a merge candidate or an inter-prediction that is generated based on the merge candidate. The video codec enables the first coding mode and disables one or more other coding modes in the particular set of coding modes. The disabled one or more coding modes in the particular set of coding modes are disabled without parsing syntax elements for the disabled coding modes. The video codec encodes or decodes the current block by using the enabled first coding mode and bypassing the disabled coding modes.

Abstract: A method of enrolling a user at a biometric lockset is described. The method includes receiving user access information from a mobile device of an administrative user of the biometric lockset. The user access information indicates to the biometric lockset to enter an enrollment mode in which a user identity is associated with fingerprint data in a user entry within a memory of the biometric lockset. A plurality of different light codes are displayed on the lockset, each one of the plurality of light codes representative of a different state of fingerprint data capture. A message is transmitted to the mobile device, and corresponds to the light code displayed at the lockset. The completed fingerprint data is stored in association with the user identity of the user in the user entry.

Abstract: Disclosed are calibration techniques that can be implemented by a device that conducts biological tests. In certain embodiments, the device for testing a biological specimen includes a receiving mechanism to receive a carrier, a camera module arranged to capture imagery of the carrier, and a processor. Some examples of the processor can detect a calibration mode trigger. In calibration mode, the processor can divide the captured imagery into segments and selectively perform one or more calibration procedures for each segment. Then, the processor records a calibration result for each segment.

Abstract: Aspects of the disclosure provide a method. The method includes forming a structure over a substrate, and forming a spacer layer on the structure, wherein the spacer layer has a recess. The method includes forming a mask layer over the spacer layer and in the recess, the mask layer including a first layer, a second layer and a third layer. The method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and. The method includes removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.