Abstract: A method for handling a measurement configuration including: determining a measurement configuration, wherein the measurement configuration includes a measurement object and a plurality of reporting configurations; performing at least one first measurement for the measurement object, to generate at least one first measurement result; and transmitting the at least one first measurement result to a network device according to a reporting configuration of the plurality of reporting configurations in response to the reporting configuration being satisfied; wherein the plurality of reporting configurations correspond to the measurement object.

Abstract: The present invention discloses an air conditioning (AC) system with compensation and controlling method thereof. The AC system with compensation comprises an environment-adjusting unit, a temperature-detecting unit, a humidity-detecting unit, a non-delayed humidity-estimate unit and a control unit. The non-delayed humidity-estimate unit is used to derive multiple non-delayed humidity-estimate values by calculating or searching from a humidity table. The control unit is used to adjust the power of the environment-adjusting unit based on the multiple non-delayed humidity-estimate values, in order to shorten the time achieving a target-moisture value.

Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.

Abstract: A display device includes a display panel, a power integrated circuit, a comparison circuit and a selection circuit. The display panel is configured to receive a system cross voltage. The power integrated circuit is configured to provide the system cross voltage to the display panel and includes a current conversion circuit configured to convert a calibration current outputted by the display panel when displaying a calibration frame into a detection voltage. The comparison circuit is configured to compare the detection voltage with a threshold to generate a comparison result. The selection circuit is configured to determine a magnitude of the system cross voltage according to the comparison result. The power integrated circuit is configured to generate the system cross voltage according to the magnitude of the system cross voltage determined by the selection circuit to provide the system cross voltage to the display panel.

Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. A gate dielectric layer is disposed under the metal compound layer and contacts the substrate.

Abstract: A memory device includes a spin-orbit-transfer (SOT) bottom electrode, an SOT ferromagnetic free layer, a first tunnel barrier layer, a spin-transfer-torque (STT) ferromagnetic free layer, a second tunnel barrier layer and a reference layer. The SOT ferromagnetic free layer is over the SOT bottom electrode. The SOT ferromagnetic free layer has a magnetic orientation switchable by the SOT bottom electrode using a spin Hall effect or Rashba effect. The first tunnel barrier layer is over the SOT ferromagnetic free layer. The STT ferromagnetic free layer is over the first tunnel barrier layer and has a magnetic orientation switchable using an STT effect. The second tunnel barrier layer is over the STT ferromagnetic free layer. The second tunnel barrier layer has a thickness different from a thickness of the first tunnel barrier layer. The reference layer is over the second tunnel barrier layer and has a fixed magnetic orientation.

Abstract: The present invention provides a novel Lactobacillus fermentum strain, named Lactobacillus fermentum strain V3, and its use in manufacturing a pharmaceutical composition or a food composition for regulating intestinal microflora and treating and/or preventing an inflammatory diseases and/or a cancer.

Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.

Abstract: The present invention relates to the use of a novel Lactobacillus brevis ProGA28 strain, deposited in the German Collection for Microorganisms and Cell Cultures (DSMZ) under the accession number DSM 33167 on May 28, 2019. The metabolites of Lactobacillus brevis ProGA28 have the ability to improve sleep quality, can effectively reduce the time of rapid eye movement in the sleep phase, can reduce time to fall asleep, can increase total sleep time, and can increase the ratio of low waves during sleep so that sleep disorders and related complications, such as anxiety and immune system diseases, are treated.

Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

Abstract: The present invention provides a novel Streptococcus thermophilus strain ST4, and its use in manufacturing a medicament and/or food composition for treating and/or preventing an inflammatory disease and/or a cancer.

Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.

Abstract: The present disclosure relates to a pixel circuit including a light emitting element, a driving circuit, a first data storage circuit and a second data storage circuit. The driving circuit is electrically coupled to the light emitting element. The first data storage circuit is electrically coupled to the driving circuit, and is configured to transmit a first data signal to the driving circuit during a first frame period, so that the driving circuit drives the light emitting element according to the first data signal. The second data storage circuit is electrically coupled to the driving circuit, and is configured to receive a second data signal during the first frame period.

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

Abstract: Various novel concepts and schemes pertaining to non-orthogonal multiple access for wireless communications are described. A group orthogonal coded access (GOCA) scheme is introduced to reduce multi-user interference (MUI) and improve performance. A repetition division multiple access (RDMA) scheme is introduced to differentiate user equipment (UEs) by different repetition patterns. A low-density spreading (LDS) scheme is introduced to reduce MUI and improve performance.

Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.

Abstract: Aspects of the present disclosure are directed to sensing earpiece positioning relative to user's left and right ears, and to routing audio signals based on the positioning. As may be implemented with various examples, for respective earpieces that generate audible sound, positions of opposing regions of one of the earpieces are detected relative to an ear, in which the opposing regions are along a perimeter of one of the earpieces. A sensor signal indicative of the detected positions is communicated, and audio signals of respective channels are routed to the earpieces, based on the sensor signal.

Abstract: The present invention discloses an air conditioning (AC) system, which comprises an indoor ventilation device, at least one air-supply chain and at least one cascading duct. The indoor ventilation device comprises a main blower. Each of the at least one air-supply chain comprises “n” sub air-supply regions each having at least one air inlet and at least one air outlet. Each of the at least one cascading duct is used to one-by-one cascade each of the “n” sub air-supply regions by sequentially connecting with the at least one air inlet and/or the at least one air outlet of each of the “n” sub air-supply regions, wherein “n” is an integer and “n”>1 and at least one of the at least one cascading duct is a partition wall connecting any two sub air-supply regions.

Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.