Patents by Inventor Wei-Jen Chen

Wei-Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11329691
    Abstract: Various novel concepts and schemes pertaining to non-orthogonal multiple access for wireless communications are described. A group orthogonal coded access (GOCA) scheme is introduced to reduce multi-user interference (MUI) and improve performance. A repetition division multiple access (RDMA) scheme is introduced to differentiate user equipment (UEs) by different repetition patterns. A low-density spreading (LDS) scheme is introduced to reduce MUI and improve performance.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: May 10, 2022
    Inventors: Guo-Hau Gau, Ho-Chi Huang, Wei-Jen Chen, Chiou-Wei Tsai, Ju-Ya Chen, Mau-Lin Wu
  • Patent number: 11322410
    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Wei-Jen Chen, Yen-Yu Chen, Ming-Hsien Lin
  • Publication number: 20220123121
    Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. A gate dielectric layer is disposed under the metal compound layer and contacts the substrate.
    Type: Application
    Filed: December 28, 2021
    Publication date: April 21, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
  • Patent number: 11296821
    Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 5, 2022
    Assignee: MEDIATEK INC.
    Inventors: Chong-You Lee, Cheng-Yi Hsu, Maoching Chiu, Timothy Perrin Fisher-Jeffes, Ju-Ya Chen, Yen Shuo Chang, Wei Jen Chen
  • Patent number: 11251279
    Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. Agate dielectric layer is disposed under the metal compound layer and contacts the substrate.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: February 15, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
  • Patent number: 11239327
    Abstract: A high electron mobility transistor (HEMT) includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer, wherein the aluminum gallium nitride layer comprises a tensile stress. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer between the source electrode and the drain electrode. At least one silicon oxide layer is embedded in the aluminum gallium nitride layer, wherein the silicon oxide layer is formed by a flowable chemical vapor deposition, and the silicon oxide layer increases the tensile stress in the aluminum gallium nitride layer.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: February 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
  • Publication number: 20220020317
    Abstract: The present disclosure relates to a pixel circuit including a light emitting element, a driving circuit, a first data storage circuit and a second data storage circuit. The driving circuit is electrically coupled to the light emitting element. The first data storage circuit is electrically coupled to the driving circuit, and is configured to transmit a first data signal to the driving circuit during a first frame period, so that the driving circuit drives the light emitting element according to the first data signal. The second data storage circuit is electrically coupled to the driving circuit, and is configured to receive a second data signal during the first frame period.
    Type: Application
    Filed: July 6, 2021
    Publication date: January 20, 2022
    Inventors: Po-Chun LAI, Wei-Ting WU, Wei-Jen CHEN, Chi-Fu TSAO, Yung-Chih CHEN
  • Publication number: 20220013648
    Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. Agate dielectric layer is disposed under the metal compound layer and contacts the substrate.
    Type: Application
    Filed: July 23, 2020
    Publication date: January 13, 2022
    Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
  • Publication number: 20210372862
    Abstract: A sensor placement optimization device is provided, which may include a preprocessing circuit and an operational circuit. The preprocessing circuit may perform a pre-process for the sensing signals of a plurality of temperature sensors, installed on a machine tool, to generate a pre-processed data. The operational circuit may execute a normalization for the pre-processed data to generate a normalized data, perform a principal component analysis for the normalized data to generate a dimensionality-reduced data and implement a principal component regression for the dimensionality-reduced data to obtain the contributions of the temperature sensors. Then, the operational circuit may rank the temperature sensors according to the contributions thereof to generate a ranking result and execute a screening process according to the ranking result to select at least one redundant sensor from the temperature sensors; afterward, the operational circuit may remove the redundant sensor from the temperature sensors.
    Type: Application
    Filed: October 23, 2020
    Publication date: December 2, 2021
    Inventors: CHIH-CHUN CHENG, WEN-NAN CHENG, PING-CHUN TSAI, SHAO-RONG SU, YAO-HUAN LEI, WEI-JEN CHEN
  • Publication number: 20210376121
    Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.
    Type: Application
    Filed: August 15, 2021
    Publication date: December 2, 2021
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Publication number: 20210336044
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 28, 2021
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
  • Patent number: 11144282
    Abstract: A system includes an accelerator to accelerate the computations of nonlinear math functions. The accelerator includes a set of first evaluators and a set of second evaluators. Each of the first evaluators and the second evaluators is a fixed-function hardware circuit specialized for evaluating a respective nonlinear function. The system further includes a processor which decodes a math instruction in an instruction set, sends to the accelerator a signal identifying a nonlinear function corresponding to the math instruction, and receives an output of the nonlinear function from the accelerator. According to the signal, the accelerator evaluates the nonlinear function using one of the first evaluators. When the signal identifies the nonlinear function as a composite function, the accelerator additionally uses one of second evaluators on an output of the one first evaluator.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: October 12, 2021
    Assignee: MediaTek Inc.
    Inventors: Yen-Yu Chen, Wei-Jen Chen, Yu Chia Chen
  • Patent number: 11127838
    Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: September 21, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Patent number: 11119001
    Abstract: A machine tool health monitoring method which is to use a predetermined plurality of vibration sensors on a plurality of components of a machine tool and to drive motors of the machine tool to excite the machine tool using an electronic device while the health status of the machine tool is good, and then to perform a diagnostic process to obtain a characteristic cluster consisting of a plurality of modals, and then to define the characteristic cluster as a sample health characteristic cluster. The diagnostic process includes the procedures of vibration transmissibility obtaining, singular value decomposition, curve fitting and modal establishing. In addition, excite the machine tool and proceed the diagnosis process to obtain a current health characteristic cluster. Finally, the current health characteristic cluster is compared with the sample health characteristic cluster to judge whether the machine tool is healthy or not.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 14, 2021
    Assignees: NATIONAL CHUNG CHENG UNIVERSITY, TONGTAI MACHINE & TOOL CO., LTD.
    Inventors: Chih-Chun Cheng, Yu-Sheng Chiu, Wen-Nan Cheng, Ping-Chun Tsai, Yu-Hsin Kuo, Wei-Jen Chen, De-Shin Liu, Chen-Wei Chuang, Chih-Ta Wu, Wen-Peng Tseng, Wen-Chieh Kuo
  • Patent number: 11088271
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: August 10, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
  • Publication number: 20210218426
    Abstract: Wireless receiver systems and methods for user equipment are described that employ multiple receiver heads. The multiple heads can receive wireless communication signals over different receive paths from different transmission sources. The systems can scan and monitor signal quality from all receiver heads during a scheduled gap in a communication link without interfering with an ongoing communication session.
    Type: Application
    Filed: December 28, 2020
    Publication date: July 15, 2021
    Applicant: MEDIATEK Singapore Pte. Ltd.
    Inventors: Yangjian Chen, Jonathan Richard Strange, Yabo Li, Ganning Yang, Wei-Yu Lai, Wei-Jen Chen
  • Patent number: 11011430
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: May 18, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
  • Publication number: 20210134981
    Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.
    Type: Application
    Filed: December 2, 2019
    Publication date: May 6, 2021
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Publication number: 20210134993
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.
    Type: Application
    Filed: November 22, 2019
    Publication date: May 6, 2021
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
  • Publication number: 20210123830
    Abstract: A machine tool health monitoring method which is to use a predetermined plurality of vibration sensors on a plurality of components of a machine tool and to drive motors of the machine tool to excite the machine tool using an electronic device while the health status of the machine tool is good, and then to perform a diagnostic process to obtain a characteristic cluster consisting of a plurality of modals, and then to define the characteristic cluster as a sample health characteristic cluster. The diagnostic process includes the procedures of vibration transmissibility obtaining, singular value decomposition, curve fitting and modal establishing. In addition, excite the machine tool and proceed the diagnosis process to obtain a current health characteristic cluster. Finally, the current health characteristic cluster is compared with the sample health characteristic cluster to judge whether the machine tool is healthy or not.
    Type: Application
    Filed: March 5, 2020
    Publication date: April 29, 2021
    Inventors: CHIH-CHUN CHENG, YU-SHENG CHIU, WEN-NAN CHENG, PING-CHUN TSAI, YU-HSIN KUO, WEI-JEN CHEN, DE-SHIN LIU, CHEN-WEI CHUANG, CHIH-TA WU, WEN-PENG TSENG, WEN-CHIEH KUO