Patents by Inventor Wei Kang

Wei Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11742204
    Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: August 29, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Jung Hsueh, Chen-En Yen, Chin Wei Kang, Kai Jun Zhan, Wei-Hung Lin, Cheng Jen Lin, Ming-Da Cheng, Ching-Hui Chen, Mirng-Ji Lii
  • Patent number: 11721579
    Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Da Cheng, Wen-Hsiung Lu, Chin Wei Kang, Yung-Han Chuang, Lung-Kai Mao, Yung-Sheng Lin
  • Publication number: 20230223357
    Abstract: A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.
    Type: Application
    Filed: May 24, 2022
    Publication date: July 13, 2023
    Inventors: Yi-Che Chiang, Chien-Hsun Chen, Tuan-Yu Hung, Hsin-Yu Pan, Wei-Kang Hsieh, Tsung-Hsien Chiang, Chao-Hsien Huang, Tzu-Sung Huang, Ming Hung Tseng, Wei-Chih Chen, Ban-Li Wu, Hao-Yi Tsai, Yu-Hsiang Hu, Chung-Shi Liu
  • Publication number: 20230223382
    Abstract: A semiconductor package includes a lower semiconductor device, a plurality of conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The plurality of conductive pillars are disposed on the lower semiconductor device along a direction parallel to a side of the lower semiconductor device. The upper semiconductor device is disposed on the lower semiconductor device and reveals a portion of the lower semiconductor device where the plurality of conductive pillars are disposed, wherein the plurality of conductive pillars disposed by the same side of the upper semiconductor device and the upper semiconductor device comprises a cantilever part cantilevered over the at least one lower semiconductor device. The encapsulating material encapsulates the lower semiconductor device, the plurality of conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over the upper semiconductor device and the encapsulating material.
    Type: Application
    Filed: March 16, 2023
    Publication date: July 13, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo-Lung Pan, Ting Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
  • Publication number: 20230223619
    Abstract: An energy storage device and a temperature control method thereof are provided. When a temperature of a battery is lower than a preset temperature and an alternating current-direct current conversion circuit receives an alternating current input voltage, an inductance-capacitance resonance circuit and a direct current-direct current conversion circuit are controlled to use electrical energy provided by the alternating current-direct current conversion circuit to generate a resonant current to heat the battery. When the temperature of the battery is lower than the preset temperature and the alternating current-direct current conversion circuit does not receive the alternating current input voltage, the inductance-capacitance resonance circuit and the direct current-direct current conversion circuit are controlled to use electrical energy provided by the battery to generate a resonant current to heat the battery.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 13, 2023
    Applicant: Merry Electronics(Shenzhen) Co., Ltd.
    Inventors: Yung-Hsiang Liu, Wei-Kang Liang, Yu-Kai Wang
  • Patent number: 11696574
    Abstract: A spinning reel includes a reel body, a handle shaft rotatably supported with respect to the reel body, a spool shaft movably supported in a front-rear direction with respect to the reel body, a reciprocator including a first gear configured to rotate in a first direction of rotation in conjunction with rotation of the handle shaft, a second gear including a gear body configured to mesh with the first gear and a first boss portion protruding from the gear body and configured to rotate in a second direction of rotation opposite to the first direction of rotation, and a slider mounted on the spool shaft and including an engagement groove with which the first boss portion is configured to engage, and a limiter disposed between the reel body and the second gear and being configured to limit rotation of the second gear in the first direction of rotation.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: July 11, 2023
    Assignee: SHIMANO COMPONENTS (MALAYSIA) SDN. BHD.
    Inventors: Foong Wei Kang, Chan Yik Hui, Mohd Hisyamuddin Bin Kamn
  • Publication number: 20230211952
    Abstract: A warehouse picking system and a warehouse picking method are provided. The warehouse picking system includes multiple cargo management stations and a management device. The management device receives multiple orders including at least one cargo, calculates an order score of each order by using an order score function; selects at least one order as a target order according to the order scores so as to determine a target cargo management station adapted for processing the target order; selects a cargo picking box storing at least one cargo in the target order from the cargo picking boxes of the target cargo management station to serve as candidate cargo picking boxes; and determines a target cargo picking box adapted for picking the cargo in the target order according to a workload of cargo picking equipment, a workload of cargo transportation equipment, and a disposition of each candidate cargo picking box.
    Type: Application
    Filed: January 25, 2022
    Publication date: July 6, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Li-Yi Liu, Po-Yu Huang, Wei-Kang Liang
  • Patent number: 11690919
    Abstract: Endolysosomal targeting conjugates that are engineered to deliver cargo molecules such as cytotoxic drugs or imaging labels with improved efficiency to late endosomes and/or lysosomes in target cells such as tumor cells are described. The endolysosomal targeting conjugate includes a targeting component and a cargo component. The targeting component is configured to bind to a cell surface molecule of a target cell and the cargo component includes a cargo molecule. The targeting component and the cargo component may be fused by a covalent bond or associated by a non-covalent bond. The targeting component may bind to the cell surface molecule or the cargo component with higher affinity in the extracellular space than in an endolysosomal compartment of the target cell.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: July 4, 2023
    Assignees: The Texas A&M University System, Board of Regents of the University of Texas System
    Inventors: Elizabeth Sally Ward Ober, Raimund Johannes Ober, Jeffrey Che-Wei Kang, Wei Sun, Ran Li
  • Publication number: 20230207297
    Abstract: In a sampling interface for mass spectrometry, a method and apparatus are set forth for preventing liquid overflow from a sampling probe into a sample. The apparatus comprises a substrate adapted to retain a droplet of liquid as it forms at an open end of the sampling probe, and a sensor on a surface of the substrate opposite the sample adapted to detect the droplet of liquid and generate a signal for controlling the droplet of liquid before it overflows into the sample.
    Type: Application
    Filed: May 22, 2021
    Publication date: June 29, 2023
    Inventors: Wan Ee ANG, Wayne Sng Wei KANG
  • Publication number: 20230206813
    Abstract: A display driving integrated circuit (IC) and a driving parameter adjustment method thereof are provided. The display driving IC includes a control circuit and a driving parameter determination circuit. The control circuit controls a current driving circuit and a scanning circuit according to a driving parameter, wherein the current driving circuit is suitable for driving multiple driving lines of a light emitting diode (LED) array, and the scanning circuit is suitable for driving multiple scanning lines of the LED array. The driving parameter determination circuit is coupled to the control circuit to provide the driving parameter. The driving parameter determination circuit dynamically adjusts the driving parameter for a target LED in the LED array according to a grayscale value of the target LED.
    Type: Application
    Filed: August 11, 2022
    Publication date: June 29, 2023
    Applicant: Novatek Microelectronics Corp.
    Inventors: Chun-Wei Kang, Yi-Yang Tsai, Siao-Siang Liu, Shih-Hsuan Huang
  • Patent number: 11682626
    Abstract: A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Wei-Kang Hsieh, Shih-Wei Chen, Tin-Hao Kuo, Hao-Yi Tsai
  • Publication number: 20230172154
    Abstract: The invention relates to a composition and method for controlling odor in pet litters. The composition includes a benzoic acid, a Generally Regarded as Safe acid, and a wetting liquid. This composition is capable of acting both as an antimicrobial and as an odor controlling preservative in pet litters. The benzoic acid and the liquid can be mixed together, or added to the litter materials, to combat the malodors created by the pet litter content.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 8, 2023
    Inventors: Mai Le Phuong HA, Ivan Wei Kang ONG
  • Publication number: 20230170443
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, active devices and transparent conductive patterns. The active devices are formed on the semiconductor substrate. The transparent conductive patterns are formed over the active devices and electrically connected to the active devices. The transparent conductive patterns are made of a metal oxide material. The metal oxide material has a first crystalline phase with a prefer growth plane rich in oxygen vacancy, and has a second crystalline phase with a prefer growth plane poor in oxygen vacancy.
    Type: Application
    Filed: January 31, 2023
    Publication date: June 1, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-En Yen, Ming-Da Cheng, Mirng-Ji Lii, Wen-Hsiung Lu, Cheng-Jen Lin, Chin-Wei Kang, Chang-Jung Hsueh
  • Patent number: 11646296
    Abstract: A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo-Lung Pan, Ting Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
  • Publication number: 20230130348
    Abstract: A holographic microscope configured to observe a sample is provided. The holographic microscope includes a light source, a light splitting element, a polarizing element, a phase modulation element, a light combining element, and a photosensitive element. The light source is configured to provide an illumination beam. The illuminating beam is transmitted through the light splitting element to form a first light beam and a second light beam, and the sample is disposed on a transmission path of the first light beam. The polarizing element and the phase modulation element are disposed on the transmission path of the first light beam or the second light beam. The first light beam and the second light beam are transmitted to the light combining element to form an interference beam. The photosensitive element is disposed on a transmission path of the interference beam to receive the interference beam to generate an optical signal.
    Type: Application
    Filed: January 20, 2022
    Publication date: April 27, 2023
    Applicant: Industrial Technology Research Institute
    Inventor: Wei-Kang Chang
  • Patent number: 11632499
    Abstract: A multi-camera positioning and dispatching system includes a plurality of cameras and processing device. The cameras are disturbed over an indoor space having a plurality of areas; the cameras are corresponding to the areas and capture the images of the areas respectively. The processing device converts the pixel coordinates of the image of the camera corresponding to each area into the camera coordinates of the area, and converts the cameras coordinates of the area into the world coordinates of the area so as to integrate the images with one another and obtain a panoramic map, defined by a world coordinate system, of the indoor space. The processing device projects the working unit in the image captured by any one of the cameras to the panoramic map. The system can achieve positioning function via the panoramic map so as to optimize indoor environment management and save manpower.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: April 18, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Li-Yi Liu, Po-Yu Huang, Wei-Kang Liang, Song-Lin Li
  • Publication number: 20230075600
    Abstract: Techniques for training and using a neural network to make predictions using trajectory modelling are disclosed herein. In some embodiments, a computer-implemented method comprises: training a first neural network with a first machine learning algorithm using training data, the first neural network being a recurrent neural network, the training data including a plurality of reference career trajectories, each reference career trajectory in the plurality of reference career trajectories comprising a sequence of reference career segments, each reference career segment in the sequence of reference career segments comprising reference profile data and reference time data indicating a position of the reference career segment within the sequence of reference career segments, the training data also including a corresponding set of reference skills for each reference career segment.
    Type: Application
    Filed: September 7, 2021
    Publication date: March 9, 2023
    Inventors: Yiming Ma, Lili Zhang, Wei Kang, Jaewon Yang
  • Publication number: 20230066410
    Abstract: A semiconductor package has central region and peripheral region surrounding central region. The semiconductor package includes dies, encapsulant, and redistribution structure. The dies include functional die and first dummy dies. Functional die is disposed in central region. First dummy dies are disposed in peripheral region. Redistribution structure is disposed on encapsulant over the dies, and is electrically connected to functional die. Vacancy ratio of central region is in the range from 1.01 to 3.00. Vacancy ratio of the peripheral region is in the range from 1.01 to 3.00. Vacancy ratio of central region is a ratio of total area of central region to total area occupied by dies disposed in central region. Vacancy ratio of peripheral region is a ratio of total area of peripheral region to total area occupied by first dummy dies disposed in peripheral region.
    Type: Application
    Filed: November 6, 2022
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Kang Hsieh, Hao-Yi Tsai, Tin-Hao Kuo, Shih-Wei Chen
  • Publication number: 20230063726
    Abstract: An integrated circuit structure includes a semiconductor substrate, a passivation layer, a first protective layer, and a second protective layer. The passivation layer is over the semiconductor substrate. The first protective layer is over the passivation layer. The second protective layer is over the first protective layer, wherein a boundary of the first protective layer is confined within the second protective layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ching Chao, Wei-Han Chiang, Peng-Yuan Jung, Chin-Wei Kang, Cheng-Jen Lin
  • Patent number: D984711
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: April 25, 2023
    Assignee: Zhongpusen Technology (Zhuzhou) Co., Ltd.
    Inventors: Bruce Pi, Wei Kang, Ren Zhong, Cong Yi