Abstract: A semiconductor structure includes a substrate, first and second transistors, first and second fuses, a contact structure, and a dielectric layer. The substrate has first and second device regions, and a fuse region. The first and second transistors are respectively above the first and second device regions. The first fuse is electrically connected to the first transistor and includes a first fuse active region having first and second portions. The second fuse is electrically connected to the second transistor and includes a second fuse active region having third and fourth portions. The contact structure interconnects the second portion and the third portion, wherein the first portion and the fourth portion are on opposite sides of the contact structure. The dielectric layer is between the contact structure and the fuse region of the substrate.

Abstract: The present disclosure provides a device including a first conductive line and a second conductive line. The first conductive line includes a first segment that extends along a first direction and has a first side forming a first angle smaller than the right angle with the first direction. The second conductive line includes a first segment deviating from the first direction with the first angle. The first segment of the second conductive line is separated from the first side of the first segment of the first conductive line by a first distance greater than or equal to a first design rule distance.

Abstract: The present disclosure relates to a thermoplastic pulverulent composition comprising (a) at least one silica particle treated with alkoxysilane; and (b) at least one thermoplastic polymer. The present disclosure also relates to a 3D-printed object formed from the thermoplastic pulverulent composition and a process of forming the 3D-printed object. The thermoplastic pulverulent composition shows good powder flowability and the printed object obtained from said thermoplastic pulverulent composition surprisingly shows high elongation at break, high impact strength, good toughness and low surface roughness.

Abstract: A semiconductor structure includes a substrate, an anti-fuse, first and second transistors, a contact structure, and a dielectric layer. The substrate includes a well region and first and second conductivity type doped regions in the well region, in which the second conductivity type doped region surrounds the first conductivity type doped region and includes a first portion and a second portion perpendicular to the first portion in a top view. The anti-fuse is in an anti-fuse region of the first conductivity type doped region. The first and second transistors are in the well region. The anti-fuse is disposed between the first and second transistors, and the anti-fuse is electrically connected to the first and second transistors. The contact structure is above the anti-fuse. The dielectric layer is between the contact structure and the anti-fuse region of the first conductivity type doped region.

Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a transistor disposed over the substrate; and a trench fuse disposed in the substrate and penetrating a source/drain (S/D) region of the transistor. A method for manufacturing the semiconductor structure is also provided.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a transistor disposed over the substrate; and a trench fuse disposed in the substrate and penetrating a source/drain (S/D) region of the transistor. A method for manufacturing the semiconductor structure is also provided.

Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having an active area and a fuse component. The fuse component has a bottom electrode in the active area, a first dielectric layer on the active area and a top electrode on the first dielectric layer. The semiconductor device also includes a second dielectric layer on the active area and surrounding the first dielectric layer.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a substrate having an active area and forming a first diffusion area in the active area. The method also includes disposing a nitride layer on the active area and forming an opening in the nitride layer to expose the first diffusion area. The method also includes disposing an oxide layer in the opening to contact the first diffusion area.

Abstract: A semiconductor structure including a semiconductor substrate, an active area, a transistor gate, a fuse gate, a first dielectric pattern, a second dielectric pattern and a plurality of metal lines is provided. The active area is disposed in the semiconductor substrate. The transistor gate has a first line segment and a second line segment extending across the active area in a first direction. The fuse gate located between the first line segment and the second line segment extends across the active area in the first direction. The first dielectric pattern is disposed between the active area and the transistor gate. The second dielectric pattern is disposed between the active area and the fuse gate. The metal lines disposed on two opposite sides of the transistor gate are electrically connected to the active device.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

Abstract: The present application discloses a semiconductor device, including a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a gate structure positioned on the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an inter-dielectric layer on a substrate; a conductive pad in the inter-dielectric layer; and a multi-stacking carrier structure including a first tier on the inter-dielectric layer, a second tier on the first tier, and a third tier on the second tier.

Abstract: A multi-stacking carrier structure includes an etch stop layer; a first tier comprising a first passivation layer positioned on the etch stop layer, a first insulating layer positioned on the first passivation layer, and a first via positioned along the first passivation layer and the first insulating layer; a second tier positioned on the first tier and comprising a second passivation layer positioned on the first insulating layer, a second insulating layer positioned on the second passivation layer, and a second via positioned along the second passivation layer and the second insulating layer, and electrically connected to the first via; and a third tier positioned on the second tier and comprising a third passivation layer positioned on the second insulating layer, a third insulating layer positioned on the third passivation layer, and a third via positioned along the third passivation layer and the third insulating layer.

Abstract: The present application provides a method for manufacturing a semiconductor device including a merged active area (AA). The method includes forming a fuse gate structure over the active area; forming a device gate structure over the active area and adjacent to the fuse gate structure; and forming a contact plug coupled to the active area and extending away from the substrate. The fuse gate structure and the device gate structure are parallel and are formed over the active area.

Abstract: The present application provides a memory device. The memory device includes a semiconductor substrate including an isolation structure and an active area surrounded by the isolation structure; a fuse gate structure disposed over the active area; a device gate structure disposed over the active area and adjacent to the fuse gate structure; and a contact plug coupled to the active area and extending away from the semiconductor substrate, wherein at least a portion of the active area is disposed under the device gate structure. Further, a method of manufacturing the memory device is also disclosed.

Abstract: A semiconductor wafer includes a scribe line and a probe pad. The scribe line extends along a first direction. The probe pad is disposed on the scribe line and is configured to contact a probe needle. The probe pad includes a first metal layer, a dielectric layer, and a second metal layer. The dielectric layer is disposed on the first metal layer, in which the dielectric layer includes a first recess and a second recess. The second metal layer is configured to connect to the first metal layer, in which the second metal layer includes a first portion and a second portion, and the first portion and the second portion are separated by a distance in a second direction perpendicular to the first direction.

Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive region positioned in the substrate; a first gate structure positioned on the substrate; a first drain region positioned in the substrate and adjacent to one sidewall of the first gate structure; and a first extended conductive region positioned in the substrate, under the first drain region, contacting a bottom surface of the first drain region, and distant from the bottom conductive region. A top surface of the first drain region and a top surface of the substrate are substantially coplanar. The bottom conductive region and the first extended conductive region include the same electrical type. The first drain region and the first extended conductive region include different electrical types.