Abstract: A lighting apparatus includes a base plate, a driver module, a light source, a mechanical switch, a main housing, and a manual switch. The driver module is disposed on a top surface of the base plate. The light source is also disposed on the top surface of the base plate. The mechanical switch is disposed on the base plate. The mechanical switch has multiple states to be selected. The driver reads a selected state to control the light source. The main housing encloses the base plate. The manual switch is disposed on the main housing. An operating part of the manual switch is exposed outside the main housing to be operated by a user. When a user moves the operating part of the manual switch, the connecting part of the manual switch carries the mechanical switch to change the selected state.

Abstract: In one embodiment, a transistor has a drift region that is formed to have a plurality of zones having different vertical doping profiles across the zones. At least one of the zones has a vertical doping profile that has a first peak near a top surface of the zone and a second peak near a bottom surface. An embodiment may have a lower doping in a region that is between the two peaks.

Abstract: In one embodiment, a transistor has a drift region that is formed to have a plurality of zones having different vertical doping profiles across the zones. At least one of the zones has a vertical doping profile that has a first peak near a top surface of the zone and a second peak near a bottom surface. An embodiment may have a lower doping in a region that is between the two peaks.

Abstract: An embodiment of a semiconductor device may include a transistor having a first doped region and a second doped region that extend laterally underlying the source, body, and drain of the transistor. The transistor may have an embodiment that includes an additional bias contact to apply a bias potential to the first doped region and or alternately the second doped region.

Abstract: An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.

Abstract: In one embodiment, a transistor has a drift region that is formed to have a plurality of zones having different vertical doping profiles across the zones. At least one of the zones has a vertical doping profile that has a first peak near a top surface of the zone and a second peak near a bottom surface. An embodiment may have a lower doping in a region that is between the two peaks.

Abstract: An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.

Abstract: An embodiment of a semiconductor device may include a transistor having a first doped region and a second doped region that extend laterally underlying the source, body, and drain of the transistor. The transistor may have an embodiment that includes an additional bias contact to apply a bias potential to the first doped region and or alternately the second doped region.

Abstract: An electronic device can include a JFET that can include a drain contact region, a channel region spaced apart from the drain contact region, and a gate region adjacent the channel region. In an embodiment, the gate region includes a relatively heavier doped portion and a relatively lighter portion closer to the drain contact region. In another embodiment, a gate field electrode can be extended beyond a field isolation structure and overlie a channel of the JFET. In a further embodiment, a region having relatively low dopant concentration can be along the drain side of the conduction path, where the region is between two other more heavily doped regions. In another embodiment, alternating conducting channel and gate regions can be used to allow lateral and vertical pinching off of the conducting channel regions.

Abstract: An electronic device can include a JFET that can include a drain contact region, a channel region spaced apart from the drain contact region, and a gate region adjacent the channel region. In an embodiment, the gate region includes a relatively heavier doped portion and a relatively lighter portion closer to the drain contact region. In another embodiment, a gate field electrode can be extended beyond a field isolation structure and overlie a channel of the JFET. In a further embodiment, a region having relatively low dopant concentration can be along the drain side of the conduction path, where the region is between two other more heavily doped regions. In another embodiment, alternating conducting channel and gate regions can be used to allow lateral and vertical pinching off of the conducting channel regions.

Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.

Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.

Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.

Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.

Abstract: A memory system has a memory array divided into a plurality of sub-arrays in which each sub-array has a mutually exclusive power domain, task scheduler circuitry coupled to the memory array, and sub-array power control circuitry coupled to the task scheduler circuitry. A method includes selecting, by the task scheduler circuitry, a task for execution, providing a control signal to the sub-array power control circuitry indicative of a set of sub-arrays to power based on the selected task, and setting a power state of each sub-array, by the sub-array control circuitry, in response to the control signal.

Abstract: A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.

Abstract: A method of forming a semiconductor device using a substrate includes forming a first select gate over the substrate, a charge storage layer over the first select gate, over the second select gate, and over the substrate in a region between the first select gate and the second select gate, wherein the charge storage layer is conformal, and a control gate layer over the charge storage layer, wherein the control gate layer is conformal. The method further includes performing a first implant that penetrates through the control gate layer in a middle portion of the region between the first select gate and the second select gate to the substrate to form a doped region in the substrate in a first portion of the region between the first select gate and the second select gate that does not reach the first select gate and does not reach the second select gate.

Abstract: Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.