Abstract: A clock receiver is provided. A receiving unit receives a pair of complementary clocks and generates a first clock, and a calibration unit detects whether a cross point of the complementary clocks has shifted, generates a detected result and accordingly adjusts toggling of the first clock.

Abstract: A variable focus device is adapted for focusing an image on an image sensing module, and includes a hollow fixing seat, a lens module and a lens coupling unit. The fixing seat is adapted for mounting the image sensing module therein. The lens coupling unit includes a piezoelectric layer and a metal layer disposed on the piezoelectric layer. The piezoelectric and metal layers are respectively formed with aligned lens mounting holes to permit mounting of the lens module to the lens coupling unit. The lens coupling unit is disposed relative to the fixing seat such that the lens module corresponds in position to the fixing seat. The piezoelectric layer deforms in response to application of a control signal thereto to move the lens module relative to the fixing seat, thereby varying a focal position of the lens module relative to the image sensing module in the fixing seat.

Abstract: The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock for extracting a period of the input clock to generate a pulse, and the digital signal generator is coupled to the pulse generator for converting the pulse into a plurality of logic values. The digital signal generator includes: a delay module coupled to the pulse, for delaying the pulse to generate a plurality of delayed pulses according to a plurality of delay amounts, respectively; and a sampling module coupled to the delay module for sampling the pulse to generate the logic values according to the delayed pulses, respectively. The decoder is coupled to the digital signal generator for determining the frequency of the input clock according to the logic values.

Abstract: Semiconductor circuit capable of selecting a corresponding adjusting parameter to adjust the received signal according to different voltages and frequencies. A voltage detector detects a voltage level of an external power voltage to generate a voltage detection signal, a frequency detector detects frequency of a main clock to generate a frequency detection signal, and a signal adjustment unit receives a first signal and selects one of a plurality of different adjusting parameters to adjust the first signal according to the voltage detection signal and the frequency detection signal.

Abstract: An apparatus for controlling a switch module in a memory is disclosed. A first pulse width adjusting unit receives an input instruction signal and adjusts a pulse width of the input instruction signal to generate an adjusted input instruction signal according to a first pulse width adjustment. A decoder receives an input address signal and the adjusted input instruction signal to generate a control signal utilized for controlling a turn-on period of the switch module. A second pulse width adjusting unit receives the control signal and adjusts a pulse width of the control signal to generate an adjusted control signal according to a second pulse width adjustment. A frequency detector controls the first and second pulse width adjusting units to set the first and second pulse width adjustments according to a frequency of a specific signal in the memory.

Abstract: An apparatus for controlling a switch module in a memory is disclosed. The apparatus includes first and second pulse width adjusting units, a decoder, and a detector. The first pulse width adjusting unit receives an input instruction signal and selectively adjusts a pulse width of the input instruction signal to generate an adjusted input instruction signal according to a first pulse width adjustment. The decoder receives an input address signal and the adjusted input instruction signal to generate a control signal to control the switch module to access data. The second pulse width adjusting unit receives the control signal and selectively adjusts a pulse width of the control signal to control the switch module according to a second pulse width adjustment. The detector detects electrical characteristic of an input signal to control the first and second pulse width adjusting units to set the first and second pulse width adjustments.

Abstract: The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock for extracting a period of the input clock to generate a pulse, and the digital signal generator is coupled to the pulse generator for converting the pulse into a plurality of logic values The digital signal generator includes: a delay module coupled to the pulse, for delaying the pulse to generate a plurality of delayed pulses according to a plurality of delay amounts, respectively; and a sampling module coupled to the delay module for sampling the pulse to generate the logic values according to the delayed pulses, respectively. The decoder is coupled to the digital signal generator for determining the frequency of the input clock according to the logic values.

Abstract: An apparatus for controlling a switch module in a memory is disclosed. The apparatus includes first and second pulse width adjusting units, a decoder, and a detector. The first pulse width adjusting unit receives an input instruction signal and selectively adjusts a pulse width of the input instruction signal to generate an adjusted input instruction signal according to a first pulse width adjustment. The decoder receives an input address signal and the adjusted input instruction signal to generate a control signal to control the switch module to access data. The second pulse width adjusting unit receives the control signal and selectively adjusts a pulse width of the control signal to control the switch module according to a second pulse width adjustment. The detector detects electrical characteristic of an input signal to control the first and second pulse width adjusting units to set the first and second pulse width adjustments.

Abstract: A phase detection method for detecting a phase difference between a data strobe signal and a clock signal, includes: latching the clock signal according to the data strobe signal to generate a phase lead/lag detection result; delaying the data strobe signal to generate a plurality of delayed data strobe signals; latching the clock signal according to the delayed data strobe signals to generate a plurality of phase detection results corresponding to the delayed data strobe signals, respectively; and if the phase lead/lag detection result indicates that the data strobe signal leads the clock signal, utilizing the phase detection results to represent the phase difference between the data strobe signal and the clock signal. A memory control method and a memory control circuit respectively corresponding to the phase detection method are further provided.

Abstract: An apparatus for controlling a switch module in a memory is disclosed. A first pulse width adjusting unit receives an input instruction signal and adjusts a pulse width of the input instruction signal to generate an adjusted input instruction signal according to a first pulse width adjustment. A decoder receives an input address signal and the adjusted input instruction signal to generate a control signal utilized for controlling a turn-on period of the switch module. A second pulse width adjusting unit receives the control signal and adjusts a pulse width of the control signal to generate an adjusted control signal according to a second pulse width adjustment. A frequency detector controls the first and second pulse width adjusting units to set the first and second pulse width adjustments according to a frequency of a specific signal in the memory.

Abstract: A memory control circuit includes: a phase detection module for detecting a phase difference between a data strobe signal and a clock signal; a control module, coupled to the phase detection module, for generating a set of control signals according to the phase difference, where the set of control signals correspond to the phase difference; a latch module for latching write data carried by a data signal according to rising/falling edges of the data strobe signal; an odd/even data separator, coupled to the latch module, for performing odd/even data separation on the write data to generate a data separation signal carrying odd/even data corresponding to the write data; and an adjustable delay line module, coupled to the odd/even data separator and the control module, for adjusting the odd/even data's delay according to the control signals, where the delay amount of the odd/even data corresponds to the control signals.

Abstract: The present invention discloses a latency counter applied to a memory, for delaying a memory accessing control signal. The latency counter includes: a clock delay module for applying at least one delay amount to the input clock to generate a delayed input clock; a frequency detector for detecting a frequency of a specific signal of the memory to set the delay amount; and a delay control signal generating module for generating a first delayed control signal and a second delayed control signal corresponding to the delayed input clock and the memory accessing control signal respectively, wherein timing of the first delayed control signal is earlier than timing of the second delayed control signal.

Abstract: The present invention is to provide a device and a method of sample rate conversion for digital image. With the present invention, the alias effect caused by shrinking the image and the blurred effect caused by enlarging the image will be eliminated. The device of the present invention comprises a ratio-adjustable expander used to receive image signal, increase the sample rate of the image M times based on the adjusting ratio for the image to generate a expanding signal; a low pass filter (LPF) used to receive the expanding signal from the expander, filter out the high rate and output the filtered signal; and a fix ratio decimator used to receive the filtered signal, low down the sample rate by N times and generate the output signal. The value of M will be changed with the adjusting ratio while the value of the N is fixed. The LPF includes the factor 1+z−1+ . . . +z−(N−1) and the factor 1+z−1+ . . . +z−(M−1).

Abstract: A device in U-shape has two plates, one lower one upper, by which the vertical bar of a handrail can be welded. It can increase the stability of the handrail on the one hand, and the plates can be adjusted to match the location of the lower end of the vertical bar on the other hand.