Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a first contact structure formed over a first side of the first S/D structure, and a portion of the first contact structure is lower than a top surface of the first S/D structure. The semiconductor structure includes a second contact structure formed over a second side of the first S/D structure, and the second contact structure is in direct contact with the first contact structure.

Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.

Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.

Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.

Abstract: Various embodiments of the present disclosure are directed towards an imaging device including a first image sensor element and a second image sensor element respectively comprising a pixel unit disposed within a semiconductor substrate. The first image sensor element is adjacent to the second image sensor element. A first micro-lens overlies the first image sensor element and is laterally shifted from a center of the pixel unit of the first image sensor element by a first lens shift amount. A second micro-lens overlies the second image sensor element and is laterally shifted from a center of the pixel unit of the second image sensor element by a second lens shift amount different from the first lens shift amount.

Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.

Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.

Abstract: A battery pack for an information handling system includes a battery cell configured to provide current to the information handling system, and a battery management unit including an output to the information handling system. The output provides a maximum continuous current (MCC) indication and a peak power (PP) indication. The battery management unit determines an amount of current that the battery cell provides to the information handling system and determines an optimum MCC value that the battery cell can provide to the information handling system. The battery management unit further provides a first value on the PP indication, the first value being greater than the optimum MCC value, sums the amount of current provided to the information handling system that is in excess of the optimum MCC value, determines that the sum is greater than a threshold, and provides a second value on the PP indication, the second value being less than the optimum MCC value.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors disposed within a substrate. The substrate comprises a front-side surface opposite a back-side surface. An outer isolation structure is disposed in the substrate and laterally surrounds the plurality of photodetectors. The outer isolation structure has a first height. An inner isolation structure is spaced between sidewalls of the outer isolation structure. The inner isolation structure is disposed between adjacent photodetectors in the plurality of photodetectors. The outer isolation structure and the inner isolation structure respectively extend from the back-side surface toward the front-side surface. The inner isolation structure comprises a second height less than the first height.

Abstract: A semiconductor device includes channel region, first and second two-dimensional metallic contacts, a gate structure, and first and second metal contacts. The channel region includes a two-dimensional semiconductor material. The first two-dimensional metallic contact is disposed at a side of the channel region and includes a two-dimensional metallic material. The second two-dimensional metallic contact is disposed at an opposite side of the channel region and includes the two-dimensional metallic material. The gate structure is disposed on the channel region in between the first and second two-dimensional metallic contacts. The first metal contact is disposed at an opposite side of the first two-dimensional metallic contact with respect to the channel region. The second metal contact is disposed at an opposite side of the second two-dimensional metallic contact with respect to the channel region.

Abstract: A semiconductor device includes channel region, first and second two-dimensional metallic contacts, a gate structure, and first and second metal contacts. The channel region includes a two-dimensional semiconductor material. The first two-dimensional metallic contact is disposed at a side of the channel region and includes a two-dimensional metallic material. The second two-dimensional metallic contact is disposed at an opposite side of the channel region and includes the two-dimensional metallic material. The gate structure is disposed on the channel region in between the first and second two-dimensional metallic contacts. The first metal contact is disposed at an opposite side of the first two-dimensional metallic contact with respect to the channel region. The second metal contact is disposed at an opposite side of the second two-dimensional metallic contact with respect to the channel region.

Abstract: A semiconductor device includes channel region, first and second two-dimensional metallic contacts, a gate structure, and first and second metal contacts. The channel region includes a two-dimensional semiconductor material. The first two-dimensional metallic contact is disposed at a side of the channel region and includes a two-dimensional metallic material. The second two-dimensional metallic contact is disposed at an opposite side of the channel region and includes the two-dimensional metallic material. The gate structure is disposed on the channel region in between the first and second two-dimensional metallic contacts. The first metal contact is disposed at an opposite side of the first two-dimensional metallic contact with respect to the channel region. The second metal contact is disposed at an opposite side of the second two-dimensional metallic contact with respect to the channel region.

Abstract: A method includes depositing a copper layer over a first substrate, annealing the copper layer, depositing a hexagonal boron nitride (hBN) film on the copper layer, and removing the hBN film from the copper layer. The hBN film may be transferred to a second substrate.

Abstract: A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.