Abstract: A low-ohmic chip resistor with high conductivity is fabricated. The chip resistor has an electrode of a base metal or base-metal alloy. The base-metal or base-metal-alloy electrode and a resistor layer are fabricated through thick-film printing with sintering at a low temperature in the air. Therein, a thick-film paste made of a cheap low-reduction-potential metal (such as aluminum (Al) or nickel (Ni)) is formed through screen-printing and sintering. Then, the layer of the cheap low-reduction-potential metal is used as a sacrificial layer to be immersed in a metal solution having a high reduction potential. Therein, a wet chemical alternation reaction is processed for obtaining a metal electrode having the high reduction potential. Or, the sacrificial layer may be immersed in a mixed solution of several different metal having high reduction potential to process wet chemical alternation reaction for obtaining an alloy of metal mixed with different composition.

Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.

Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.

Abstract: A thick-film copper paste is made. A displacement reaction with low cost is used to precipitate nano-silver (Ag) to be grown on copper particles. Thus, the thick-film copper paste is made of the copper powder coated with nano-Ag. The paste can be sintered in the air and is increased in overall electrical conductivity. The copper inside is not oxidized. Its resistance on electromigration is good. Furthermore, the paste can be added with frit as a sintering aid to assist sintering the nano-Ag-coated copper paste. Furthermore, even in a high-temperature heat treatment, the powder of nano-Ag-coated copper is still antioxidant and can replace the silver paste used in the current market.

Abstract: A fabrication method of magnetic device is provided. A magnetic material is provided. A portion of the magnetic material is selectively irradiated by an energy beam, and reactive gas is introduced simultaneously. The magnetic material being irradiated is melted and solidified to form a solidified layer. An outer layer of the solidified layer reacts with the reactive gas to form a barrier layer, so as to form a magnetic unit including the solidified layer and the barrier layer. It is determined whether the manufacturing process of the same layer is finished, if not, the energy beam is moved to the other portion of the magnetic material. The above step is repeated to overlap multiple magnetic units to form a magnetic layer. If yes, the flow returns to the 1st step to provide another magnetic material to the magnetic layer. The above steps are repeated to form a 3D magnetic device.

Abstract: The present invention provides an aluminum (Al) paste. The Al paste has low cost and high conductivity. An Al powder having a wide range of particle size distribution and an increased solid content are used to solve the problem of multiple pores. A rupture mechanism of alumina is fully used for sintering to improve contacting internal liquid Al with each other for forming conductive paths. With coordination of sufficient liquid glass powder, all ruptured surface of the Al powder is coated to inhibit exposed liquid Al from oxidation on contacting air. The problem of low conductivity of Al paste is thus radically solved.

Abstract: A chip resistor having terminal electrodes is provided. In the chip resistor, a first protector layer has a size different from that of a first resistor layer. Thus, two ends of the first resistor layer are exposed to form new current conduction path. Original current conduction path having the same size of the protective layer and the resistor layer is thus replaced. Hence, resistance variation of the chip resistor is solved; yield of the chip resistor is increased; and, the material cost of the front terminal electrode is greatly reduced.

Abstract: A chip resistor having terminal electrodes is provided. In the chip resistor, a first protector layer has a size different from that of a first resistor layer. Thus, two ends of the first resistor layer are exposed to form new current conduction path. Original current conduction path having the same size of the protective layer and the resistor layer is thus replaced. Hence, resistance variation of the chip resistor is solved; yield of the chip resistor is increased; and, the material cost of the front terminal electrode is greatly reduced.

Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.

Abstract: A semiconductor device and method of formation are provided. A semiconductor device includes a copper fill over a first layer in a first opening. The first layer includes cobalt and tungsten. A third layer including cobalt and tungsten is over the copper fill and the first layer. The first layer including cobalt and tungsten has a smoother sidewall than a first layer that does not have cobalt or tungsten. A smoother sidewall decreases defects in the copper fill, thus increasing conductivity of the copper fill. The first layer and the third layer reduce out diffusion of copper from the copper fill as compared to a semiconductor device that does not comprise such layers.

Abstract: A method of manufacturing an order vacancy compound (OVC) is provided. The method includes the following steps. A trivalent ion, a hexavalent ion and one of a univalent ion and a bivalent ion for an electrodeposition process are provided to form a solar energy absorbing film. The OVC is formed by performing an electrochemical etching process on the solar energy absorbing film.

Abstract: A self-forming barrier structure and a semiconductor device using the same are disclosed. The self-forming barrier structure includes a silicon-containing substrate; a first barrier layer formed on the silicon-containing substrate; and a second barrier layer formed of a copper-containing alloy on the first barrier layer; wherein the copper-containing alloy comprises copper and at least one other metal which diffuses faster than copper and is not inter-miscible with copper.

Abstract: A method of manufacturing an order vacancy compound (OVC) is provided. The method includes the following steps. A trivalent ion, a hexavalent ion and one of a univalent ion and a bivalent ion for an electrodeposition process are provided to form a solar energy absorbing film. The OVC is formed by performing an electrochemical etching process on the solar energy absorbing film.

Abstract: Electronic devices with hybrid high-k dielectric and fabrication methods thereof. The electronic device includes a substrate. A first electrode is disposed on the substrate. Hybrid high-k multi-layers comprising a first dielectric layer and a second dielectric layer are disposed on the substrate, wherein the first dielectric layer and the second dielectric layer are solvable and substantially without interface therebetween. A second electrode is formed on the hybrid multi-layers.

Abstract: Electronic devices with hybrid high-k dielectric and fabrication methods thereof. The electronic device includes a substrate. A first electrode is disposed on the substrate. Hybrid high-k multi-layers comprising a first dielectric layer and a second dielectric layer are disposed on the substrate, wherein the first dielectric layer and the second dielectric layer are solvable and substantially without interface therebetween. A second electrode is formed on the hybrid multi-layers.

Abstract: Electronic devices with hybrid high-k dielectric and fabrication methods thereof. The electronic device includes a substrate. A first electrode is disposed on the substrate. Hybrid high-k multi-layers comprising a first dielectric layer and a second dielectric layer are disposed on the substrate, wherein the first dielectric layer and the second dielectric layer are solvable and substantially without interface therebetween. A second electrode is formed on the hybrid multi-layers.

Abstract: The present invention mainly relates to a method for reducing shrinkage during sintering low-temperature-cofired ceramics, the ceramics comprising a dielectric portion and a heterogeneous material portion, the method comprising the steps of: (a) providing a monolithic structure, the monolithic structure comprising a dielectric body and a constraining layer; the dielectric body comprising at least one dielectric layer that comprises at least one active area; wherein said active area is disposed with at least one heterogeneous material pattern; the constraining layer positioned on the top of the dielectric body comprising at least one window wherein the edge of the active area of the dielectric layer each falls within the edge of the window in the vertical direction; (b) firing the monolithic structure; and (c) singulating the monolithic structure along a cutting line to provide the low-temperature-cofired ceramics, wherein the cutting line is disposed in the area formed between the edge of the window and the e

Abstract: The present invention relates to a novel ZnTiO3-based dielectric material, having the composition represented by the formula (Zn1-aMga)(Ti1-b-cMnbDc)dO3, wherein D is an element having a valence of 5 or above, 0?a?0.5, c?b?0.1, 0<c?0.1, 1?d?1.5, which has properties of ultra low sintering temperature, high reliability, and high dielectric strength, and is capable of being applied to produce low capacitance multilayer ceramic capacitor with high quality factor, low ESR, and high insulation resistance. The present invention also relates to a method of preparing such a novel ZnTiO3-based dielectric material.

Abstract: The present invention relates to a novel ZnTiO3-based dielectric material, having the composition represented by the formula (Zn1-aMga)(Ti1-b-cMnbDc)dO3, wherein D is an element having a valence of 5 or above, 0?a?0.5, c?b?0.1, 0<c?0.1, 1?d?1.5, which has properties of ultra low sintering temperature, high reliability, and high dielectric strength, and is capable of being applied to produce low capacitance multilayer ceramic capacitor with high quality factor, low ESR, and high insulation resistance. The present invention also relates to a method of preparing such a novel ZnTiO3-based dielectric material.

Abstract: The present invention provides a multilayer ceramic composition comprising at least one layer of dielectric material M1 and at least one layer of dielectric material M2, wherein passive components are buried in both layers of dielectric material M1 and M2 that prevent each other from shrinkage in the X and Y dimensions during firing. Each layer of the multilayer ceramic composition according to the invention can be used as a substrate for burying the passive component and has the ability to prevent other layer with different dielectric constant from shrinkage. Hence, the multilayer ceramic composition has the advantages of smaller size and a better circuit precision.