Abstract: Antenna diodes used to correct antenna rule violations during the design and formation of integrated circuits are defined within filler cells laid out on the IC chip following the layout of standard electronic module cells and routing of electrical conductors on the chip. The filler cells are disposed in gaps between standard cells containing the electronic modules. The diodes are formed in unconnected pairs that are selectively connected to each other and to an adjacent conductor in order to correct antenna rule violations. Low current leakage is achieved as a result of the use of a fewer number of diode circuits, and the fact that they remain unconnected until used to correct an antenna rule violation.

Abstract: Antenna diodes used to correct antenna rule violations during the design and formation of integrated circuits are defined within filler cells laid out on the IC chip following the layout of standard electronic module cells and routing of electrical conductors on the chip. The filler cells are disposed in gaps between standard cells containing the electronic modules. The diodes are formed in unconnected pairs that are selectively connected to each other and to an adjacent conductor in order to correct antenna rule violations. Low current leakage is achieved as a result of the use of a fewer number of diode circuits, and the fact that they remain unconnected until used to correct an antenna rule violation.

Abstract: A dynamic-floating-gate arrangement is used to improve the ESD robustness of driving-current-programmable CMOS output buffers in cell libraries, by suitably dynamically floating the gates of the NMOS/PMOS buffers using a small-dimension CMOS device having its drain connected to the gate of an unused CMOS buffer, its source connected to one of two voltage sources, and its gate connected between a resistance, that is connected between the two voltage sources, and a capacitance connected between the resistance and the same one of the two voltage sources as the source of the small-dimension CMOS device.

Abstract: A programmable non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate, whose first input terminal is coupled to receive an inverted signal of the primary clock signal. Further, the first input terminal of a second logic gate is coupled to receive the primary clock signal. A first programmable delay means, connected between an output of the first logic gate and the second input terminal of the second logic gate, is used to delay an output signal from the first logic gate a predetermined amount of time according to the selection signal.