Patents by Inventor Wen-Ming Chen
Wen-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10720360Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.Type: GrantFiled: December 9, 2016Date of Patent: July 21, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen
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Publication number: 20200152506Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.Type: ApplicationFiled: January 13, 2020Publication date: May 14, 2020Inventors: Yu-Sheng TANG, Fu-Chen CHANG, Cheng-Lin HUANG, Wen-Ming CHEN, Chun-Yen LO, Kuo-Chio LIU
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Publication number: 20200105654Abstract: A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.Type: ApplicationFiled: June 21, 2019Publication date: April 2, 2020Inventors: Ling-Wei Li, Cheng-Lin Huang, Min-Tar Liu, Fu-Kang Chiao, Matt Chou, Chun-Yen Lo, Che-Jung Chu, Wen-Ming Chen, Kuo-Chio Liu
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Patent number: 10535554Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.Type: GrantFiled: October 5, 2017Date of Patent: January 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Sheng Tang, Fu-Chen Chang, Cheng-Lin Huang, Chun-Yen Lo, Wen-Ming Chen, Kuo-Chio Liu
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Patent number: 10510605Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.Type: GrantFiled: July 24, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen
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Patent number: 10312118Abstract: A bonding apparatus includes a wafer stage, a first chip stage, a first chip transporting device, a second stage and a second chip transporting device. The wafer stage is used for holding a wafer. The first chip stage is used for holding at least one first chip. The first chip transporting device is used for transporting the first chip from the first chip stage onto the wafer. The second chip stage is used for holding at least one second chip. The second chip transporting device is used for transporting the second chip from the second chip stage onto the wafer.Type: GrantFiled: January 16, 2014Date of Patent: June 4, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Shan Wu, Yi-Ting Hu, Ming-Tan Lee, Yu-Lin Wang, Yuh-Sen Chang, Pin-Yi Shin, Wen-Ming Chen, Wei-Chih Chen, Chih-Yuan Chiu
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Publication number: 20190131263Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.Type: ApplicationFiled: December 19, 2018Publication date: May 2, 2019Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
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Publication number: 20190103389Abstract: Present disclosure provides a method for forming a semiconductor packaged wafer, including providing a semiconductor package having a die on a first side of a wafer, partially molding the die by disposing molding material on the first side of the wafer, a peripheral of the first side is free of molding material at a completion of the partially molding, and bonding the semiconductor package with a carrier from the first side of the wafer. Present disclosure also provides a semiconductor packaged wafer, including a die on a first side of a wafer, a molding encapsulating the die and partially positioning on the first side of the wafer by retracting from a peripheral of the first side of the wafer, and a sealing structure on the peripheral of the first side of the wafer.Type: ApplicationFiled: February 21, 2018Publication date: April 4, 2019Inventors: FU-CHEN CHANG, CHENG-LIN HUANG, WEN-MING CHEN, SHIH-YEN CHEN, RUEI-YI TSAI, PIN-YI HSIN
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Patent number: 10163836Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.Type: GrantFiled: January 22, 2018Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
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Publication number: 20180330991Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.Type: ApplicationFiled: July 24, 2018Publication date: November 15, 2018Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen
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Patent number: 10014218Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor structure. The semiconductor structure has a central portion and a peripheral portion surrounding the central portion. The method includes forming first conductive bumps and dummy conductive bumps over a surface of the semiconductor structure. The first conductive bumps are over the central portion and electrically connected to the semiconductor structure. The dummy conductive bumps are over the peripheral portion and electrically insulated from the semiconductor structure. The first conductive bumps each have a first thickness and a first width. The dummy conductive bumps each have a second thickness and a second width. The second thickness is less than the first thickness. The second width is greater than the first width.Type: GrantFiled: April 20, 2017Date of Patent: July 3, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Fu Shih, Cheng-Lin Huang, Chien-Chen Li, Che-Jung Chu, Wen-Ming Chen, Kuo-Chio Liu
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Publication number: 20180166328Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.Type: ApplicationFiled: October 5, 2017Publication date: June 14, 2018Inventors: Yu-Sheng TANG, Fu-Chen CHANG, Cheng-Lin HUANG, Chun-Yen LO, Wen-Ming CHEN, Kuo-Chio LIU
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Publication number: 20180166409Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.Type: ApplicationFiled: January 22, 2018Publication date: June 14, 2018Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
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Publication number: 20180033695Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.Type: ApplicationFiled: December 9, 2016Publication date: February 1, 2018Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen
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Patent number: 9875979Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.Type: GrantFiled: November 16, 2015Date of Patent: January 23, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
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Patent number: 9748130Abstract: A method includes setting a first tension value of a laminating tape during a standby mode. A second tension value of the laminating tape is set during taping on a wafer. The second tension value is different from the first tension value. A third tension value of the laminating tape is set after taping. The third tension value is different from the second tension value.Type: GrantFiled: November 29, 2013Date of Patent: August 29, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Ming Chen, Wei-Chih Chen, Tung-Hsiao Yu, Min-Yu Wu
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Publication number: 20170141059Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.Type: ApplicationFiled: November 16, 2015Publication date: May 18, 2017Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
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Publication number: 20150200118Abstract: A bonding apparatus includes a wafer stage, a first chip stage, a first transporting device, a second stage and a second transporting device. The wafer stage is used for holding a wafer. The first chip stage is used for holding at least one first chip. The first transporting device is used for transporting the first chip from the first chip stage onto the wafer. The second chip stage is used for holding at least one second chip. The second transporting device is used for transporting the second chip from the second chip stage onto the wafer.Type: ApplicationFiled: January 16, 2014Publication date: July 16, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Shan WU, Yi-Ting HU, Ming-Tan LEE, Yu-Lin WANG, Yuh-Sen CHANG, Pin-Yi SHIN, Wen-Ming CHEN, Wei-Chih CHEN, Chih-Yuan CHIU
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Publication number: 20150155195Abstract: A method includes setting a first tension value of a laminating tape during a standby mode. A second tension value of the laminating tape is set during taping on a wafer. The second tension value is different from the first tension value. A third tension value of the laminating tape is set after taping. The third tension value is different from the second tension value.Type: ApplicationFiled: November 29, 2013Publication date: June 4, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Ming Chen, Wei-Chih Chen, Tung-Hsiao Yu, Min-Yu Wu
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Patent number: 8859246Abstract: The invention discloses a method for production of polyhydroxybutyrate-co-polyhydroxyvalerate (PHBV) by recombinant Escherichia coli harboring plasmid containing both phaCAB and prpE. Different percentage of hydroxyvalerate can be obtained from the recombinant E. coli when cultivated in the medium containing different concentrations of propionic acid. In this patent, we provide a method that integrated all of the genes (i.e. phaCAB, vgb and prpE) required for PHBV production into a single plasmid. The plasmids were then transformed into an E. coli host. Results showed that PHBV can be produced by this recombinant E. coli, and the ration of HV to HB in the co-polymers can be regulated by addition of different concentrations of propionic acid in the medium. The percentage of HV in the co-polymers can be adjusted from about 3% up to more than 35%.Type: GrantFiled: May 29, 2012Date of Patent: October 14, 2014Assignee: Yuan Ze UniversityInventors: Chih-Ching Chien, Po-Chi Soo, Yu-Tze Horng, Shan-Yu Chen, Hsiu-Hsiung Li, Yu-Hong Wei, Wen-Ming Chen