Patents by Inventor Wen Wang

Wen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967717
    Abstract: Disclosed is a tungsten-doped lithium manganese iron phosphate-based particulate for a cathode of a lithium-ion battery. The particulates include a composition represented by a formula of LixMn0.998-y-zFeyMzW0.002PaO4a±p/C, wherein x, y, z, a, p, and M are as defined herein. Also disclosed is a powdery material including the particulates, and a method for preparing the powdery material.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: April 23, 2024
    Assignee: HCM CO., LTD.
    Inventors: Chien-Wen Jen, Hsin-Ta Huang, Chih-Tsung Hsu, Yi-Hsuan Wang
  • Patent number: 11968817
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Publication number: 20240122982
    Abstract: A chimeric antigen receptor fusion protein co-expressing IL-7 and CCR2b, and application thereof are provided. The fusion protein includes a chimeric antigen receptor, a 2A peptide, IL-7, a 2A peptide and CCR2b which are sequentially linked in series.
    Type: Application
    Filed: March 30, 2021
    Publication date: April 18, 2024
    Inventors: Guangchao LI, Min LUO, Wen DING, Xuejun WANG
  • Publication number: 20240124043
    Abstract: A wheeled carrying apparatus includes a frame structure including a standing frame, a wheel mount carrying a wheel and pivotally connected with the standing frame, the wheel being rotatable relative to the first wheel mount about a wheel axis, a locking assembly including a wheel mount latch movably connected with the standing frame, the wheel mount latch being engaged with the wheel mount to rotationally lock the first wheel mount with respect to the standing frame, and disengaged from the wheel mount to unlock the wheel mount for rotation of the wheel mount to change an orientation of the wheel axis, an actuating assembly coupled to the wheel mount latch and including one or more linking part, and a release mechanism including an operating part provided on the frame structure that is operable to cause the actuating assembly to pull the wheel mount latch to disengage from the wheel mount.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 18, 2024
    Inventors: Leilei ZHENG, Zheng-Wen GUO, Er Xue WANG, Mingxing SUN, Shoufeng HU, Wanquan ZHU
  • Publication number: 20240122956
    Abstract: The present disclosure relates to the field of medicine and specifically to an application of naringin combined with rapamycin in preparation of medications for treating hyperlipidemia. Naringin achieves anti-inflammatory and lipid-lowering effects by inhibiting the formation of oxLp-NLRP3 complexes. The present disclosure has been substantiated through cellular experiments and animal experiments, it demonstrates that naringin effectively intervenes in the early progression of hyperlipidemia by neutralizing oxLp and inhibiting the formation of oxLp-NLRP3 complexes. The inhibitory effect of naringin on oxLp-NLRP3 complexes contributes to unleashing the therapeutic potential of rapamycin in hyperlipidemia, providing a combined strategy for the prevention and treatment of hyperlipidemia-related diseases in clinical applications.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: AIR FORCE MEDICAL UNIVERSITY
    Inventors: Lina Niu, Kaiyan Wang, Weiwei Yu, Wen Qin, Yuxuan Ma, Chen Lei
  • Patent number: 11961769
    Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 11962847
    Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: April 16, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chia-Hao Chang, You-Tsai Jeng, Kai-Wen Yeh, Yi-Cheng Chen, Te-Chuan Wang, Kai-Wen Cheng, Chin-Lung Lin, Tai-Lai Tung, Ko-Yin Lai
  • Patent number: 11961768
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Publication number: 20240119200
    Abstract: A method of building a characteristic model includes: acquiring raw electrical data from a measurement system outside one or more processing units; acquiring operational state-related data from an information collector inside the one or more processing units; performing a data annealing process on the raw electrical data and the operational state-related data to obtain and purified electrical data and purified operational state-related data; and performing a machine learning (ML)-based process to build the characteristic model based on the purified electrical data and the purified operational state-related data.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 11, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Jen Chen, Chien-Chih Wang, Wen-Wen Hsieh, Ying-Yi Teng
  • Publication number: 20240119613
    Abstract: A structured-light three-dimensional (3D) scanning system includes a projector that emits a projected light with a predetermined pattern onto an object; an image capture device that generates a captured image according to a reflected light reflected from the object, the predetermined pattern of the projected light being distorted due to 3D shape of the object, thereby resulting in a distorted pattern; a depth decoder that converts the distorted pattern into a depth map representing the 3D shape of the object; and a depth fusion device that generates a fused depth map according to at least two different depth maps associated with the object.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 11, 2024
    Inventors: Hsueh-Tsung Lu, Ching-Wen Wang, Cheng-Che Tsai, Wu-Feng Chen
  • Publication number: 20240120317
    Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.
    Type: Application
    Filed: July 13, 2023
    Publication date: April 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
  • Patent number: 11955379
    Abstract: A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Wen Wu, Chun-I Tsai, Chi-Cheng Hung, Jyh-Cherng Sheu, Yu-Sheng Wang, Ming-Hsing Tsai
  • Patent number: 11956948
    Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen Su, Yu-Kuan Lin, Shih-Hao Lin, Lien-Jung Hung, Ping-Wei Wang
  • Patent number: 11955335
    Abstract: In a method of coating a photo resist over a wafer, dispensing the photo resist from a nozzle over the wafer is started while rotating the wafer, and dispensing the photo resist is stopped while rotating the wafer. After starting and before stopping the dispensing the photo resist, a wafer rotation speed is changed at least 4 times. During dispensing, an arm holding the nozzle may move horizontally. A tip end of the nozzle may be located at a height of 2.5 mm to 3.5 mm from the wafer.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung-Hung Feng, Hui-Chun Lee, Sheng-Wen Jiang, Shih-Che Wang
  • Patent number: 11953235
    Abstract: A low-heat-loss operation method of a line-focusing heat collection system and the line-focusing heat collection system are provided. The method includes the following steps. Solar energy is utilized to preheat a collector tube in an empty tube state, so that the collector tube is in a preheating mode. After a set preheating temperature is reached, a heat transfer working medium is injected into the collector tube. In the injection process of the heat transfer working medium, an injection section of the collector tube is converted into a focusing mode from a preheating mode. After heat collection is finished, the circulation of the heat transfer working medium is stopped, and the focusing mode of the collector tube is kept. In the drainage process of the heat transfer working medium, an emptying section of the collector tube is converted into a light heat-tracing mode from a focusing mode.
    Type: Grant
    Filed: August 31, 2023
    Date of Patent: April 9, 2024
    Assignees: Lanzhou Dacheng Technology Co., Ltd., Dunhuang Dacheng Shengneng Technology Co., Ltd.
    Inventors: Duowang Fan, Duojin Fan, Linggang Kong, Wenye Qi, Yulei Fan, Xiaoming Yao, Zhiyong Zhang, Bo Li, Fujun Zhao, Zhilin Liu, Guodong Wang, Wen Li, Chongchong Zhang
  • Publication number: 20240114688
    Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 4, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Ling Hsiu Chou, Jen Yang Hsueh, Chih-Yang Hsu
  • Patent number: 11945877
    Abstract: Antibodies, antigen-binding fragments and polypeptides that bind to HER2 are disclosed, as well as nucleic acids and vectors encoding the same. Also provided are cells comprising the antibodies, antigen-binding fragments, polypeptides, nucleic acids and vectors, methods of making such molecules, and the use of such molecules for therapeutic applications.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: April 2, 2024
    Assignee: Agency for Science, Technology and Research
    Inventors: Cheng-I Wang, Lionel Jianrong Low, Angeline Goh, Sandy Wen-Hsin Lee
  • Patent number: 11945772
    Abstract: A method including the step contacting an olefin, an alcohol, a metallosilicate catalyst and a solvent, wherein the solvent comprises structure (I): wherein R1 and R2 are each selected from the group consisting of an aryl group and an alkyl group with the proviso that at least one of R1 and R2 is an aryl group, further wherein n is 1-3.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: April 2, 2024
    Assignee: Dow Global Technologies LLC
    Inventors: Wen-Sheng Lee, Mingzhe Yu, Jing L. Houser, Sung-Yu Ku, Wanglin Yu, Stephen W. King, Paulami Majumdar, Le Wang
  • Patent number: 11949868
    Abstract: Embodiments of the present disclosure provide a method and device for selecting a context model of a quantized coefficient end flag. The method comprises: obtaining a scanning position POS of a non-zero coefficient corresponding to current quantized coefficient end flag in a specific scanning order; wherein the scanning position POS is a subscript of the non-zero coefficient in the scanning order; configuring a first context model array, and using a fixed value as the base to calculate the logarithmic value of the value of the scanning position POS plus 1, and according to the logarithmic value, selecting a first context model from the first context model array; and using the first context model to encode or decode a binary symbol of the current quantized coefficient end flag. According to the technical solution of the present application, it is able to improve encoding and decoding efficiency for a quantized coefficient end flag, thereby further improve the efficiency of video encoding and decoding.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 2, 2024
    Assignee: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOL
    Inventors: Ronggang Wang, Zhenyu Wang, Wen Gao
  • Patent number: 11949526
    Abstract: Presented herein is a stage area for “focused” video that is configured to allow for dynamic layout changes during an online video conference or meeting. By providing a user interface environment that allows a user (meeting participant) to customize the stage, each participant can choose their own view, and the meeting host can fully customize a view for every participant in the meeting.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: April 2, 2024
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Yun Teng, Wen Jiang, Shujun Han, Yiqun Wang, Lin Wang