Abstract: The present invention generally relates to provide a fabrication method of a flash memory with L-shaped floating gate. The present invention utilizes a dielectric spacer on a surface of a semiconductor substrate to form a L-shaped poly spacer, which is so called the L-shaped floating gate. The respective inside portion of L-shaped floating gate is gibbous and to form a tip structure. Then, an isolating dielectric layer and a control gate are formed thereon. The control gate is covering the gibbous tip structure of the L-shaped floating gate to complete a flash memory device. The present invention is provided with a channel length, which is stably and easily controlled, and a tip structure for point discharging. Hence, the present invention can enhance the isolating effect between the control gate and the floating gate to achieve the purpose of repeating control the fabrication of the semiconductor devices.

Abstract: The present invention generally relates to a method for fabricating a post-process one-time programmable (OTP) read only memory cell (ROM cell). The OTP ROM cell has two oxide layers positioned on a semiconductor substrate and a plurality of semiconductor-implanted regions are implanted in the semiconductor substrate. Oxide layers are respectively to those semiconductor-implanted regions of the semiconductor substrate and having a window-type isolating channel region for each. Finally, a polysilicon layer is positioned on the thicker oxide layer as a gate electrode region of the OTP ROM cell. Hence, the polysilicon layer can be applied a voltage to penetrate the thinker oxide layer of the window-type isolating channel region to form a P-N junction between the semiconductor-implanted regions and the polysilicon layer and then the ROM cell is programmed.

Abstract: The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.

Abstract: The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.

Abstract: The present invention provides a fabrication method of devices like flash memory cells, which is used to fabricate a poly spacer as a floating gate. In the present invention, an oxide, a predefined and patterned first dielectric, a first poly silicon, and a second dielectric are formed in order on the surface of a semiconductor substrate. Next, anisotropic etch is performed to the second dielectric to form dielectric spacer around projective sides of the first poly silicon. The first poly silicon is then etched with the dielectric spacer as a mask. Subsequently, the first dielectric is removed. A poly spacer is thus completed. The poly spacer is used as a floating gate to complete a flash memory. A channel length of stability and easy control and tips useful for point discharge can thus be obtained so that repetitive control of fabrication of semiconductor devices can be achieved.

Abstract: The present invention provides a fabrication method of devices like flash memory cells, which is used to fabricate a poly spacer as a floating gate. In the present invention, an oxide, a predefined and patterned first dielectric, a first poly silicon, and a second dielectric are formed in order on the surface of a semiconductor substrate. Next, anisotropic etch is performed to the second dielectric to form dielectric spacer around projective sides of the first poly silicon. The first poly silicon is then etched with the dielectric spacer as a mask. Subsequently, the first dielectric is removed. A poly spacer is thus completed. The poly spacer is used as a floating gate to complete a flash memory. A channel length of stability and easy control and tips useful for point discharge can thus be obtained so that repetitive control of fabrication of semiconductor devices can be achieved.

Abstract: The present invention provides a method of making an ID code of ROM and a structure thereof, wherein an ROM code is implanted into channel regions between a plurality of bit lines and the region covered by a plurality of word lines on a semiconductor substrate. A field oxide for marking is situated at a predetermined position of the semiconductor substrate. A mark layer is attached on the surface of the field oxide using material different from oxide. The mark layer has a set of mark numbers to form an ID code structure. The formed ID code of the present invention can be clearly identified.

Abstract: The present invention provides a method of making an ID code of ROM and a structure thereof, wherein an ROM code is implanted into channel regions between a plurality of bit lines and the region covered by a plurality of word lines on a semiconductor substrate. A field oxide for marking is situated at a predetermined position of the semiconductor substrate. A mark layer is attached on the surface of the field oxide using material different from oxide. The mark layer has a set of mark numbers to form an ID code structure. The formed ID code of the present invention can be clearly identified.

Abstract: The present invention relates to a memory cell structure of a flash memory and a method for fabricating the same and, more particularly, to a flash memory having annular floating gates. The present invention uses the capacitance coupling between the source and the floating gate to form a channel in the substrate under the floating gate. Hot electrons are injected into the floating gate or released from the floating gate to the control gate through inerpoly dieletric by injection point on the top of floating gate In the proposed memory cell, a floating gate is etched to form an annular shape situated between a drain, a source, and two field oxides. An interpoly dielectric and a control gate are stacked in turn on the floating gate and on the surface of the substrate not covered by the floating gate through means of self-alignment. An injection point not covered by the SiN film of the interpoly dielectric is formed on the top of the floating gate.

Abstract: In a traditional ROM semiconductor process, ROM codes are performed by ion implantation. Due to the limitations of ion implantation energy and threshold control, the implantation for program codes must be performed before forming an inter-layer oxide layer. Therefore, the required delivery time of the process becomes longer. The invention provide a method of manufacturing ROMs that can shorten delivery time by using only one mask to simultaneously form program codes and contact windows.

Abstract: An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, wherein the current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.

Abstract: An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, wherein the current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.

Abstract: The present invention relates to a memory cell structure of a flash memory and a method for fabricating the same and, more particularly, to a flash memory having circumventing floating gates and a method for fabricating the same. In the proposed memory cell, a floating gate and a tunneling oxide are etched to form an annular shape situated between a drain, a source, and two field oxides. An interpoly dielectric and a control gate cover in turn on the floating gate and on the surface of the substrate not covered by the floating gate by means of self-alignment. The present invention can not only achieve self-alignment to form the control gate and apply to high-integration memory cells with small areas, but also can effectively increase the high capacitance coupling ratio thereof to enhance the tunneling effect of hot electrons.

Abstract: The present invention relates to a memory cell structure of a flash memory and a method for fabricating the same and, more particularly, to a flash memory having annular floating gates. The present invention uses the capacitance coupling between the source and the floating gate to form a channel in the substrate under the floating gate. Hot electrons are injected into the floating gate or released from the floating gate to the control gate through inerpoly dieletric by injection point on the top of floating gate In the proposed memory cell, a floating gate is etched to form an annular shape situated between a drain, a source, and two field oxides. An interpoly dielectric and a control gate are stacked in turn on the floating gate and on the surface of the substrate not covered by the floating gate through means of self-alignment. An injection point not covered by the SiN film of the interpoly dielectric is formed on the top of the floating gate.

Abstract: An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, wherein the current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.

Abstract: The present invention provide a method for reducing the sheet resistance of the buried layer serving as the bit line or an interconnect of a semiconductor device. The method includes steps of providing the silicon substrate, doping the silicon substrate for forming an extrinsic silicon region, and forming a silicide layer on the extrinsic silicon region for obtaining a low-resistance buried layer.

Abstract: A method is provided for manufacturing a memory cell with a increased threshold voltage accuracy. The memory cell has a substrate including a plurality of first conducting lines in a first direction and a plurality of second conducting lines in a second direction. The method includes the steps of forming a photoresist layer over the first and the second conducting lines, forming a window on the photoresist layer to expose a portion of the second conducting lines, thinning the portion of the second conducting lines in the windows, and doping impurities into the substrate between two of the first conducting lines to form the memory cell.

Abstract: A high Q inductor and its forming method is disclosed. In this forming method, a semiconductor substrate is first provided with a trench formed thereon. The trench is defined by dry etching and formed to a depth of 3˜5 &mgr;m. A material having a higher resistivity than that of the semiconductor is then provided to fill the trench. The material can be formed by first depositing an epitaxy layer with a lower dopant concentration than that of the semiconductor substrate by several orders of magnitude on the semiconductor substrate, then etching back the epitaxy layer to expose the surface of the semiconductor substrate. Thereafter, a dielectric layer is formed on the semiconductor substrate and the trench, and an inductor winding is formed on the dielectric layer above the trench to form the high Q inductor.

Abstract: A method for forming an inductor in a semiconductor substrate having a trench therein including the steps of forming a first metal portion in the trench, providing a flowable dielectric material in the trench, depositing a layer of dielectric material over the layer of first metal portion and flowable dielectric material, forming a plug in the layer of dielectric material wherein the plug is in electrical contact with the first metal portion, and forming a second metal portion over the layer of dielectric material wherein the second metal portion is in electrical contact with the plug.

Abstract: This invention discloses a memory cell that has a first polysilicon, which functions as a gate. The memory cell further includes a first TEOS oxide layer overlying the first polysilicon and a plurality of via-1 openings exposing the first polysilicon therein. The memory cell further includes a patterned second polysilicon layer overlying the first TEOS oxide layer and filling the via-1 openings thus contacting the gate wherein the patterned second polysilicon containing dopant ions for functioning as a connector for the memory cell. The memory cell further includes a second TEOS oxide layer overlying the connector includes a plurality of via-2 openings for exposing the connector therein. The memory cell further includes a silicide barrier layer disposed in the via-2 openings.