Patents by Inventor Werner Graf
Werner Graf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20080315326Abstract: An integrated circuit having an active semiconductor device is formed comprising a trench defined by conductor lines previously formed.Type: ApplicationFiled: June 21, 2007Publication date: December 25, 2008Inventors: Werner Graf, Ines Uhlig, Daniel Koehler, Joerg Radecker, Lars Heineck
-
Publication number: 20080150141Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate with a main surface; forming a wiring metal layer above said main surface; forming a doped getter layer on said wiring metal layer; and forming at least one additional wiring metal layer on said doped getter layer. The present invention also provides a corresponding integrated semiconductor structure and a semiconductor memory device.Type: ApplicationFiled: January 11, 2007Publication date: June 26, 2008Inventors: Werner Graf, Andreas Thies, Marco Lepper, Momtchil Stavrev
-
Patent number: 7361974Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a sacrificial plug made of a first material surrounded by an isolation layer between two adjacent gate stacks in the first region; depositing a planarisation layer over said plurality of gate stacks in said first region and said at least one gate stack in said second region; backpolishing said planarisation layer such that the upper surface of said sacrificial plug is exposed; forming a structured hardmask layer made of said first material on said backpolished planarisation layer which structured hardmask layer adjoins said sacrificial plug and has at least one opening in said second region; forming at least one contact hole in said second region under said at least one opening in said second region, said at least one contact hole exposing a substraType: GrantFiled: March 23, 2006Date of Patent: April 22, 2008Assignee: Infineon Technologies AGInventor: Werner Graf
-
Patent number: 7314803Abstract: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.Type: GrantFiled: November 18, 2005Date of Patent: January 1, 2008Assignee: Infineon Technologies AGInventors: Werner Graf, Lars Heineck, Jana Horst
-
Publication number: 20070224810Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a sacrificial plug made of a first material surrounded by an isolation layer between two adjacent gate stacks in the first region; depositing a polarization layer over said plurality of gate stacks in said first region and said at least one gate stack in said second region; backpolishing said polarization layer such that the upper surface of said sacrificial plug is exposed; forming a structured hardmask layer made of said first material on said backpolished polarization layer which structured hardmask layer adjoins said sacrificial plug and has at least one opening in said second region; forming at least one contact hole in said second region under said at least one opening in said second region, said at least one contact hole exposing a substrateType: ApplicationFiled: March 23, 2006Publication date: September 27, 2007Inventor: Werner Graf
-
Patent number: 7217610Abstract: A method for the integration of field-effect transistors for memory and logic applications in a semiconductor substrate is disclosed. The gate dielectric and a semiconductor layer are deposited over the whole area both in the logic region and in the memory region. From these layers, the gate electrodes in the memory region are formed, the source and drain regions are implanted and the memory region is covered in a planarizing manner with an insulation material. Afterward, the gate electrodes are formed from the semiconductor layer and the gate dielectric in the logic region.Type: GrantFiled: July 30, 2002Date of Patent: May 15, 2007Assignee: Infineon Technologies AGInventors: Werner Graf, Albrecht Kieslich
-
Patent number: 7215023Abstract: A power module includes at least one carrier body for mounting at least one power component thereon, and at least one energy storage component. For this purpose, a hybrid circuit is arranged as a thick film circuit on at least one of the carrier bodies, and the hybrid circuit includes at least one thick film resistor as a discharging resistor for discharging the at least one energy storage component. The power module is adapted for use as a power converter for electric motors.Type: GrantFiled: November 28, 2002Date of Patent: May 8, 2007Assignee: Conti Temic microelectronic GmbHInventors: Hermann Baeumel, Werner Graf, Hermann Kilian, Bernhard Wagner, Dietrich George, William T. Briggs
-
Patent number: 7208416Abstract: The invention provides a simple method of treating a structured surface comprising a higher surface in a first region and a lower surface in the second region. A plurality of layers is deposited on said surface wherein a lower layer exhibits a higher polishing rate than an upper layer and wherein the thickness of the plurality of layers exceeds the step height. Afterwards the plurality of layers is chemically mechanically polished such that the lower layer is at least partly removed in the first region. By this method achieves a better planarization. Additionally, smaller top contact openings after a wet clean step are achievable and a deformation of contact openings due to annealing steps is reduced.Type: GrantFiled: January 28, 2005Date of Patent: April 24, 2007Assignee: Infineon Technologies AGInventors: Matthias Kroenke, Thomas Dittkrist, Werner Graf
-
Publication number: 20060276019Abstract: The invention relates to a method for production of contacts on a wafer, preferably with the aid of a lithographic process. The preferred embodiment provides a method which overcomes the disadvantages of the complex point/hole lithography process, and which avoids any increase in the process complexity. This method is achieved in that a strip structure extending over two layers is used to structure the contacts. The strip structure in the first layer is rotated at a predetermined angle with respect to the strip structure in the second layer, and the contacts are formed in the mutually overlapping areas of the strip structures in the two layers.Type: ApplicationFiled: August 11, 2006Publication date: December 7, 2006Inventors: Werner Graf, Henning Haffner, Johannes Kowalewski, Lars Heineck
-
Patent number: 7094674Abstract: The invention relates to a method for production of contacts on a wafer, preferably with the aid of a lithographic process. The preferred embodiment provides a method which overcomes the disadvantages of the complex point/hole lithography process, and which avoids any increase in the process complexity. This method is achieved in that a strip structure extending over two layers is used to structure the contacts. The strip structure in the first layer is rotated at a predetermined angle with respect to the strip structure in the second layer, and the contacts are formed in the mutually overlapping areas of the strip structures in the two layers.Type: GrantFiled: December 18, 2003Date of Patent: August 22, 2006Assignee: Infineon Technologies AGInventors: Werner Graf, Henning Haffner, Johannes Kowalewski, Lars Heineck
-
Publication number: 20060172539Abstract: The invention provides a simple method of treating a structured surface comprising a higher surface in a first region and a lower surface in the second region. A plurality of layers is deposited on said surface wherein a lower layer exhibits a higher polishing rate than an upper layer and wherein the thickness of the plurality of layers exceeds the step height. Afterwards the plurality of layers is chemically mechanically polished such that the lower layer is at least partly removed in the first region. By this method achieves a better planarisation. Additionally, smaller top contact openings after a wet clean step are achievable and a deformation of contact openings due to annealing steps is reduced.Type: ApplicationFiled: January 28, 2005Publication date: August 3, 2006Applicant: INFINEON TECHNOLOGIES AGInventors: Matthias Kroenke, Thomas Dittkrist, Werner Graf
-
Publication number: 20060148227Abstract: A silicon dioxide layer is formed and a mask layer is deposited and then patterned to produce openings in the mask layer in the region around the gate contacts onto the gate electrode tracks in the logic region. The surface is uncovered around the gate contacts to the gate electrode tracks in the logic region, reducing the silicon dioxide layer. A sacrificial layer covering the gate electrode tracks is formed and patterned to form sacrificial layer blocks above the contact openings for the bit line contacts between the mutually adjacent gate electrode tracks in the cell array region and above the contact openings for the substrate contacts to the semiconductor surface and the gate contacts onto the gate electrode tracks in the logic region. A filling layer is formed between the sacrificial layer blocks, and the sacrificial layer blocks are removed. The contact opening regions are filled with conductive material.Type: ApplicationFiled: April 27, 2005Publication date: July 6, 2006Applicant: Infineon Technologies AGInventors: Matthias Kronke, Joachim Patzer, Werner Graf
-
Publication number: 20060141756Abstract: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.Type: ApplicationFiled: November 18, 2005Publication date: June 29, 2006Inventors: Werner Graf, Lars Heineck, Jana Horst
-
Patent number: 7018781Abstract: Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.Type: GrantFiled: March 29, 2004Date of Patent: March 28, 2006Assignee: Infineon Technologies, AGInventors: Hans-Georg Fröhlich, Oliver Genz, Werner Graf, Stefan Gruss, Matthias Handke, Percy Heger, Lars Heineck, Antje Laessig, Alexander Reb, Kristin Schupke, Momtchil Stavrev, Mirko Vogt
-
Patent number: 7009290Abstract: A heat sink for semiconductor components or similar devices, especially produced from an extruded aluminum alloy. The heat sink comprises cooling ribs which rise at a distance from a base plate and which are clamped in an insert groove made in the surface of the base plate, laterally limited by longitudinal or intermediate ribs with a coupling base that has an approximately rectangular cross-section. The coupling bases are held in their insert grooves in a form-fit and are cold-welded with the base plate at least in some sections. Cross ribs extend at a distance to one another on the surfaces of the intermediate ribs and have the form of upset heels that are linked with the coupling base in a form-fit.Type: GrantFiled: December 5, 2002Date of Patent: March 7, 2006Assignee: Alcan Technology & Management Ltd.Inventors: Uwe Bock, Werner Graf, Stephan Bock
-
Patent number: 6952347Abstract: A power module is suggested having a simple and cost-effective arrangement and ensuring a reliable operation. To this end, a circuit arrangement comprising at least one electronic component is arranged on a carrier body. A conductor pattern is formed on the top side of the carrier body, and a structured cooling element made of the material of the carrier body, is provided on the bottom side. The invention also relates to a power module as power converter for electric motors.Type: GrantFiled: December 10, 2001Date of Patent: October 4, 2005Assignee: Conti Temic microelectronic GmbHInventors: Hermann Baeumel, Werner Graf, Hermann Kilian, Bernhard Schuch
-
Patent number: 6927154Abstract: A gate structure of a transistor is fabricated with an additional barrier formed on a metal layer of the gate structure before the deposition of a silicon oxide layer. Applying this barrier layer on the metal layer before the deposition of the silicon oxide layer prevents an oxidation of the metal during the deposition of the silicon oxide layer. A lowering of the conductivity of the metal layer or a loss of metal through sublimating metal oxide is thereby prevented. As a result, in particular the performance of the gate structure or of the transistor is improved further. In addition, disturbing coupling effects in the circuit are significantly reduced by the use of the silicon oxide cap.Type: GrantFiled: May 6, 2003Date of Patent: August 9, 2005Assignee: Infineon Technologies AGInventors: Werner Graf, Ulrike Bewersdorff-Sarlette
-
Publication number: 20050168197Abstract: Proposed is a simple, economical construction, which ensures a reliable operation, of the power module comprising at least one carrier body for mounting at least one power component. For this purpose, a hybrid circuit is arranged as a thick film circuit on at least one of the carrier bodies, and the hybrid circuit comprises at least one thick film resistor as a discharging resistor for discharging at least one component provided as an energy store. Power module as a power converter for electric motors.Type: ApplicationFiled: November 28, 2002Publication date: August 4, 2005Inventors: Hermann Baeumel, Werner Graf, Hermann Kilian, Bernhard Wagner, Dietrich George, William Briggs
-
Publication number: 20050012202Abstract: A heat sink for semiconductor components or similar devices, especially produced from an extruded aluminum alloy. The heat sink comprises cooling ribs which rise at a distance from a base plate and which are clamped in an insert groove made in the surface of the base plate, laterally limited by longitudinal or intermediate ribs with a coupling base that has an approximately rectangular cross-section. The coupling bases are held in their insert grooves in a form-fit and are cold-welded with the base plate at least in some sections. Cross ribs extend at a distance to one another on the surfaces of the intermediate ribs and have the form of upset heels that are linked with the coupling base in a form-fit.Type: ApplicationFiled: December 5, 2002Publication date: January 20, 2005Inventors: Uwe Bock, Werner Graf, Stephan Bock
-
Publication number: 20050003308Abstract: In order to fabricate a contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, on a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on the semiconductor surface, an insulator layer is formed on the semiconductor surface and a sacrificial layer is subsequently formed on the insulator layer, then material plugs are produced on the sacrificial layer for the purpose of defining contact openings between the mutually adjacent gate electrode tracks, the sacrificial layer is etched to form material plugs with the underlying sacrificial layer blocks, after the production of the vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, an essentially planar surface being formed, then the sacrificial layer material is etched out from the vitreous layer and the uncovered insulator material is removed above the contact openings on the semiconductType: ApplicationFiled: March 29, 2004Publication date: January 6, 2005Applicant: Infineon Technologies AGInventors: Hans-Georg Frohlich, Oliver Genz, Werner Graf, Stefan Gruss, Matthias Handke, Percy Heger, Lars Heineck, Antje Laessig, Alexander Reb, Kristin Schupke, Momtchil Stavrev, Mirko Vogt