Patents by Inventor Werner Schustereder

Werner Schustereder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190295848
    Abstract: A semiconductor device and method is disclosed. In one example, the method for forming a semiconductor device includes forming a trench extending from a front side surface of a semiconductor substrate into the semiconductor substrate. The method includes forming of material to be structured inside the trench. Material to be structured is irradiated with a tilted reactive ion beam at a non-orthogonal angle with respect to the front side surface such that an undesired portion of the material to be structured is removed due to the irradiation with the tilted reactive ion beam while an irradiation of another portion of the material to be structured is masked by an edge of the trench.
    Type: Application
    Filed: June 14, 2019
    Publication date: September 26, 2019
    Applicant: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Anton Mauder, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 10366895
    Abstract: A semiconductor device and method is disclosed. In one example, the method for forming a semiconductor device includes forming a trench extending from a front side surface of a semiconductor substrate into the semiconductor substrate. The method includes forming of material to be structured inside the trench. Material to be structured is irradiated with a tilted reactive ion beam at a non-orthogonal angle with respect to the front side surface such that an undesired portion of the material to be structured is removed due to the irradiation with the tilted reactive ion beam while an irradiation of another portion of the material to be structured is masked by an edge of the trench.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: July 30, 2019
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Anton Mauder, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 10347491
    Abstract: Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body. Forming the contact electrode includes forming a barrier layer on sections of the semiconductor body uncovered in the at least one contact hole, wherein the barrier layer is configured to inhibit the recombination center particles from diffusing out of the semiconductor body.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 9, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Wolfgang Jantscher, Alexander Binter, Oliver Blank, Petra Fischer, Ravi Keshav Joshi, Kurt Pekoll, Manfred Pippan, Andreas Riegler, Werner Schustereder, Juergen Steinbrenner, Waqas Mumtaz Syed
  • Patent number: 10317338
    Abstract: A method of determining the carbon content in a silicon sample may include: generating electrically active polyatomic complexes within the silicon sample. Each polyatomic complex may include at least one carbon atom. The method may further include: determining a quantity indicative of the content of the generated polyatomic complexes in the silicon sample, and determining the carbon content in the silicon sample from the determined quantity.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: June 11, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Naveen Goud Ganagona, Moriz Jelinek, Helmut Oefner, Hans-Joachim Schulze, Werner Schustereder
  • Publication number: 20190123193
    Abstract: In an embodiment, a semiconductor device is provided. The semiconductor device includes: a semiconductor body of a first conductivity type having opposing first and second major surfaces; a gate arranged in a trench extending into the semiconductor body from the first major surface; a body region of a second conductivity type; a source region of the first conductivity type arranged on the body region and having first and second dopant species. The source region forms a pn-junction with the body junction, the pn-junction being arranged at a depth dpn from the first major surface, wherein 50 nm<dpn<300 nm. A drain region of the first conductivity type is arranged in the semiconductor body under the trench.
    Type: Application
    Filed: October 19, 2018
    Publication date: April 25, 2019
    Inventors: Anton Mauder, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder
  • Publication number: 20190066977
    Abstract: An ion implantation method includes changing an ion acceleration energy and/or an ion beam current density of an ion beam while effecting a relative movement between a semiconductor substrate and the ion beam impinging on a surface of the semiconductor substrate.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 28, 2019
    Inventors: Moriz Jelinek, Michael Brugger, Hans-Joachim Schulze, Werner Schustereder, Peter Zupan
  • Publication number: 20190051529
    Abstract: Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.
    Type: Application
    Filed: October 12, 2018
    Publication date: February 14, 2019
    Inventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
  • Publication number: 20190051488
    Abstract: An implantation apparatus includes a scanning assembly that effects a relative movement between an ion beam and a semiconductor substrate along a first scan direction and along a second scan direction orthogonal to the first scan direction. A tilt assembly changes a tilt angle ? between a beam axis of the ion beam and a normal to a main surface of the semiconductor substrate from a first tilt angle ?1 to a second tilt angle ?2, wherein an angular span ?? between the first tilt angle ?1 and the second tilt angle ?2 is at least 5°. A control unit controls the tilt assembly to continuously change the tilt angle ? during the relative movement between the ion beam and the semiconductor substrate.
    Type: Application
    Filed: August 7, 2018
    Publication date: February 14, 2019
    Inventors: Werner Schustereder, Moriz Jelinek, Hans-Joachim Schulze
  • Patent number: 10192955
    Abstract: A method of manufacturing a semiconductor device includes determining information that indicates an extrinsic dopant concentration and an intrinsic oxygen concentration in a semiconductor wafer. On the basis of information about the extrinsic dopant concentration and the intrinsic oxygen concentration as well as information about a generation rate or a dissociation rate of oxygen-related thermal donors in the semiconductor wafer, a process temperature gradient is determined for generating or dissociating oxygen-related thermal donors to compensate for a difference between a target dopant concentration and the extrinsic dopant concentration.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: January 29, 2019
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Moriz Jelinek, Hans-Joachim Schulze, Werner Schustereder, Michael Stadtmueller
  • Publication number: 20190013210
    Abstract: Various embodiments provide a method of reducing a sheet resistance in an electronic device encapsulated at least partially in an encapsulation material, wherein the method comprises: providing an electronic device comprising a multilayer structure and being at least partially encapsulated by an encapsulation material; and locally introducing energy into the multilayer structure for reducing a sheet resistance.
    Type: Application
    Filed: August 29, 2018
    Publication date: January 10, 2019
    Applicant: Infineon Technologies AG
    Inventors: Edward Fuergut, Irmgard Escher-Poeppel, Stephanie Fassl, Paul Ganitzer, Gerhard Poeppel, Werner Schustereder, Harald Wiedenhofer
  • Patent number: 10128328
    Abstract: Crystal lattice defects are generated in a horizontal surface portion of a semiconductor substrate and hydrogen-related donors are formed in the surface portion. Information is obtained about a cumulative dopant concentration of dopants, including the hydrogen-related donors, in the surface portion. Based on the information about the cumulative dopant concentration and a dissociation rate of the hydrogen-related donors, a main temperature profile is determined for dissociating a defined portion of the hydrogen-related donors. The semiconductor substrate is subjected to a main heat treatment applying the main temperature profile to obtain, in the surface portion, a final total dopant concentration deviating from a target dopant concentration by not more than 15%.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: November 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Hans Weber, Hans-Joachim Schulze, Johannes Georg Laven, Werner Schustereder
  • Publication number: 20180308698
    Abstract: In various embodiments, a method of processing one or more semiconductor wafers is provided. The method includes positioning the one or more semiconductor wafers in an irradiation chamber, generating a neutron flux in a spallation chamber coupled to the irradiation chamber, moderating the neutron flux to produce a thermal neutron flux, and exposing the one or more semiconductor wafers to the thermal neutron flux to thereby induce the creation of dopant atoms in the one or more semiconductor wafers.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Markus Bina, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 10109489
    Abstract: Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 23, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
  • Patent number: 10096677
    Abstract: A method for forming a semiconductor device includes implanting a predefined dose of protons into a semiconductor substrate. Further, the method comprises controlling a temperature of the semiconductor substrate during the implantation of the predefined dose of protons so that the temperature of the semiconductor substrate is within a target temperature range for more than 70% of an implant process time used for implanting the predefined dose of protons. The target temperature range reaches from a lower target temperature limit to an upper target temperature limit. Further, the lower target temperature limit is equal to a target temperature minus 30° C. and the upper target temperature limit is equal to the target temperature plus 30° C. and the target temperature is higher than 80° C.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: October 9, 2018
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Naveen Goud Ganagona, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 10083835
    Abstract: By directing an ion beam with a beam divergence ? on a process surface of a semiconductor substrate, parallel electrode trenches are formed in the semiconductor substrate. A center axis of the directed ion beam is tilted to a normal to the process surface at a tilt angle ?, wherein at least one of the tilt angle ? and the beam divergence ? is not equal to zero. The semiconductor substrate is moved along a direction parallel to the process surface during formation of the electrode trenches. A conductive electrode is formed in the electrode trenches, wherein first sidewalls of the electrode trenches are tilted to the normal by a first slope angle ?1 with ?1 =(?+?/2) and second sidewalls are tilted to the normal by a second slope angle ?2 with ?2 =(???/2).
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: September 25, 2018
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Anton Mauder, Roland Rupp, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 10074715
    Abstract: A method for forming a semiconductor device includes determining at least one electrical parameter for each semiconductor device of a plurality of semiconductor devices to be formed in a semiconductor wafer. The method further includes implanting doping ions into device areas of the semiconductor wafer used for forming the plurality of semiconductor devices with laterally varying implantation doses based on the at least one electrical parameter of the plurality of semiconductor devices.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: September 11, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Werner Schustereder, Hans-Joachim Schulze, Hans Weber
  • Publication number: 20180240672
    Abstract: A semiconductor device includes a device doping region of an electrical device arrangement disposed in a semiconductor substrate. A portion of the device doping region has a vertical dimension of more than 500 nm and a doping concentration of greater than 1*1015 dopant atoms per cm3. The doping concentration of the portion of the device doping region varies by less than 20% from a maximum doping concentration in the device doping region.
    Type: Application
    Filed: April 24, 2018
    Publication date: August 23, 2018
    Inventors: Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 10037887
    Abstract: A method for implanting ions into a semiconductor substrate includes performing a test implantation of ions into a semiconductor substrate. The ions of the test implantation are implanted with a first implantation angle range over the semiconductor substrate. Further, the method includes determining an implantation angle offset based on the semiconductor substrate after the test implantation and adjusting a tilt angle of the semiconductor substrate with respect to an implantation direction based on the determined implantation angle offset. Additionally, the method includes performing at least one target implantation of ions into the semiconductor substrate after the adjustment of the tilt angle. The ions of the at least one target implantation are implanted with a second implantation angle range over the semiconductor substrate. Further, the first implantation angle range is larger than the second implantation angle range.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: July 31, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Michael Brugger, Moriz Jelinek, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder
  • Publication number: 20180182629
    Abstract: Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body. Forming the contact electrode includes forming a barrier layer on sections of the semiconductor body uncovered in the at least one contact hole, wherein the barrier layer is configured to inhibit the recombination center particles from diffusing out of the semiconductor body.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 28, 2018
    Inventors: Wolfgang Jantscher, Alexander Binter, Oliver Blank, Petra Fischer, Ravi Keshav Joshi, Kurt Pekoll, Manfred Pippan, Andreas Riegler, Werner Schustereder, Juergen Steinbrenner, Waqas Mumtaz Syed
  • Patent number: 10002930
    Abstract: Disclosed is a method. The method includes forming a metal layer on a first surface of a semiconductor body; irradiating the metal layer with particles to move metal atoms from the metal layer into the semiconductor body and form a metal atom containing region in the semiconductor body; and annealing the semiconductor body. The annealing includes heating at least the metal atom containing region to a temperature of less than 500° C.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 19, 2018
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Jens Peter Konrath, Francisco Javier Santos Rodriguez, Carsten Schaeffer, Hans-Joachim Schulze, Werner Schustereder, Guenther Wellenzohn