Abstract: Cache replacement policy mechanism for updating cache entries of a partitioned cache using a pseudo-LRU (least recently updated) scheme for partial updating of LRU bits.

Abstract: According to one general aspect, a method of performing a cache transaction may include transmitting a cache request to a target device. The method may include receiving a cache response that is associated with the cache request. The method may further include completing the cache transaction without transmitting an exclusive cache response acknowledgement message to the target device.

Abstract: Techniques for receiving and processing detected events are provided. A bit array may be received from a device. Each bit value in the bit array may indicate whether a user initiated event relating to interaction with a website was detected by the device. Data regarding a start time associated with the bit array may be received. Each bit value in the bit array is associated with a time increment after the start time.

Abstract: A method and apparatus for selectively bypassing a cache in a processor of a computing device are disclosed. A mechanism to provide visibility to transactions on the core to a cache interface (e.g., an L3 cache interface) in a trace controller buffer (TCB) for debugging purposes, by causing selected transactions, which would otherwise be satisfied by the cache, to bypass the cache and be presented to the memory system where they may be logged in the TCB is described. In an embodiment of the invention, there is provided a method for providing processing core request visibility comprising bypassing a higher level cache in response to a processing core request, capturing the processing core request in a TCB, providing a mask to filter the processing core request, and returning a transaction response to a requesting processing core.

Abstract: A device includes a link interface circuit, a first plurality of allocated buffers, and a second plurality of non-allocated buffers. The link interface circuit is operable to communicate over a communications link using a plurality of virtual channels. A different subset of the plurality of allocated buffers is allocated to each of the virtual channels. The non-allocated buffers are not allocated to a particular virtual channel. The link interface circuit is operable to receive a first transaction over the communications link and assign the first transaction to one of the allocated buffers or one of the non-allocated buffers.

Abstract: Disclosed is an apparatus for altering the temperature of a liquid, comprising: a pipe having a first end for receiving a liquid and a second end for discharging the liquid; and a thermal element for altering the temperature of the liquid, wherein the thermal element is located in the pipe such that the volume available for the liquid within the pipe is in the range 0 to 20% of the pipe volume.

Abstract: A method for controlling data flow to a pair of storage devices includes receiving at least one new entry to store in a first storage device or a second storage device in the pair of storage devices and determining a number of entries made to the first and second storage devices out of the at least one new entry. The method also includes calculating a difference between available space in the first storage device and the second storage device, and calculating a number of credits used by the at least one new entry based on the numbers of entries to the first and second storage devices and on the difference in available space.

Abstract: A probe for measurement of water temperature profiles is disclosed herein. In various aspects, the probe may include an electronic assembly and a housing over-molded upon at least portions of the electronic assembly to sealingly enclose the portions of the electronic assembly. The electronic assembly may include a pressure sensor to measure a pressure value indicative of a water depth, and a temperature sensor to measure a water temperature value indicative of a water temperature, a communication interface. Methods of manufacture of the probe are also disclosed herein.

Abstract: System and methods are provided for reducing vibration in server or data storage units. An anti-vibration system according to the present invention includes one or more disk drives and one or more fans in a defined area, and a controller which is configured to control operation of each of the one or more fans. A nominal speed setting and a speed range are determined for the one or more fans, either commonly or independently with respect to each, and the fans are caused to be driven in accordance with the determined speed setting and speed range. As a result the occasions in which individual fan speeds are coincident with fixed frequency sensitivities for each disk drive are substantially minimized.

Abstract: A method and apparatus for accelerated shared data migration between cores, Using an Always Migrate protocol, when a migratory probe hits a directory entry in either modified or owned state, the entry is transitioned to an owned state, and a source done command is sent without sending cache block ownership or state information to the directory.

Abstract: A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.

Abstract: A processor power limiter and method is provided. The processor includes a first programmable location configured to store a processor power target. A power monitor is configured to estimate a power dissipation due to processor load. A power controller is configured to adjust a processor power parameter based on the power target and the power dissipation. The processor may include an interface for an operating system. A second programmable location may be configured to store a software processor power target accessible by the operating system. The processor may also include a sideband interface for an external agent. A third programmable location may be configured to store an agent processor power target accessible by the external agent. The power controller may be configured to adjust a processor core voltage and/or frequency such that the power dissipation stays below the processor power target, software processor power target and the agent processor power target.

Abstract: A method and apparatus for accelerated shared data migration between cores. Using an Always Migrate protocol, when a migratory probe hits a directory entry in either modified or owned state, the entry is transitioned to an owned state, and a source done command is sent without sending cache block ownership or state information to the directory.

Abstract: A man packable, portable sounding kit includes, in one example, at least two balloons and at least two radiosondes each including a tether for connecting a radiosonde to a balloon. A gas container includes gas for inflating the at least two balloons. A fill hose assembly includes a balloon inflation nozzle coupled to a pressure regulator. A data transceiver unit is configured to receive and optionally to rebroadcast atmospheric weather data from the radiosonde. A case houses the balloons, radiosondes, data transceiver unit, gas container, and fill hose assembly.

Abstract: This application describes a system that captures 3D geometry commands from a first 3D graphics process and stores them in a shared memory. A second 3D environment process creates a 3D display environment using a display and display hardware. A third process obtains the 3D commands and supplies them to the hardware to place 3D objects in the 3D environment. The result is a fused display environment where 3D objects are displayed along with other display elements. Input events in the environment are analyzed and mapped to the 3D graphics process or the environment where they affect corresponding processing.

Abstract: A system may include a device that is in a first location that is not readily accessible. The device may detect a powering up of the device a particular quantity of times during a particular time interval. Powering up of the device may be controlled from a second location that is readily accessible. The device may also be reset, in response to detecting the device being powered up the particular quantity of times during the particular time interval, to original factory settings.

Abstract: Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.

Abstract: A method and system for detecting and correcting a bad bit error in a solid-state nonvolatile memory device. The device includes a bad bit detection module that receives an old page from the memory device and determines whether a page has a bad bit. The device further includes a bad bit correction module that generates a new page, determines a location of the bad bit, determines a preferred value of the bad bit, determines a user value of the bad bit and inserts the preferred value into a string of bits corresponding to substantive data of the old page, recording the string of bits with the preferred value inserted therein and stores the new page at an address of the old page.

Abstract: A draper platform (100) has a center endless belt conveyor (118) that is supported on and between first and second adjacent support arms (246A, 246B). The center endless belt conveyor (118) is releasable from a first support arm (246A) of the two adjacent support arms to pivot downward away from the first support arm of the two adjacent support arms a distance sufficient to slidably remove an endless conveyor belt (134) from the center endless belt conveyor in a direction parallel to the axes of rotation of the rolls (300, 302) that support the endless conveyor belt.