Abstract: A system and method for managing multiple discrete operating points to create a stable virtual operating point. One or more functional blocks within a processor produces data corresponding to an activity level associated with the respective functional block. A power manager determines a power consumption value based on the data once every given sample interval. In addition, the power manager determines a signed accumulated difference over time between a thermal design power (TDP) and the power consumption value. The power manager selects a next power-performance state (P-state) based on comparisons of the signed accumulated difference and given thresholds. Transitioning between P-states in this manner while the workload does not significantly change causes the processor to operate at a virtual operating point between supported discrete operating points.

Abstract: A draper platform (100) has a center endless belt conveyor (118) that is supported on and between first and second adjacent support arms (246A, 246B). The center endless belt conveyor (118) is releasable from a first support arm (246A) of the two adjacent support arms to pivot downward away from the first support arm of the two adjacent support arms a distance sufficient to slidably remove an endless conveyor belt (134) from the center endless belt conveyor in a direction parallel to the axes of rotation of the rolls (300, 302) that support the endless conveyor belt.

Abstract: A method and apparatus are described for adjusting a bit width of an input/output (I/O) link established between a transmitter and a receiver. The I/O link has a plurality of bit lanes. The transmitter may send to the receiver a command identifying at least one selected bit lane of the I/O link that will be powered off or powered on in response to detecting that a bit width adjustment threshold of the I/O link has been reached.

Abstract: A device includes a link interface circuit, a first plurality of allocated buffers, and a second plurality of non-allocated buffers. The link interface circuit is operable to communicate over a communications link using a plurality of virtual channels. A different subset of the plurality of allocated buffers is allocated to each of the virtual channels. The non-allocated buffers are not allocated to a particular virtual channel. The link interface circuit is operable to receive a first transaction over the communications link and assign the first transaction to one of the allocated buffers or one of the non-allocated buffers.

Abstract: Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.

Abstract: A draper platform (100) has a knife drive (250) for driving a knife assembly (140) that is supported on and between two adjacent support arms (246) that pivot with respect to each other and with respect to the frame (102, 104, 106) of the draper platform (100) to which the two adjacent support arms (246A, 246B) are pivotally connected. two resilient mounts couple opposing sides fo he sub-frame to the two adjacent support arms.

Abstract: A draper platform (100) has a center endless belt conveyor (118) that is supported on and between two adjacent support arms (246A, 246B) that pivot with respect to each other and with respect to the frame (102, 104, 106) of the draper platform (100) to which the two adjacent support arms (246A, 246B) are pivotally connected.

Abstract: A draper platform (100) has a center endless belt conveyor (118) that is supported on and between two adjacent support arms (246A, 246B) that pivot with respect to each other and with respect to the frame (102, 104, 106) of the draper platform (100) to which the two adjacent support arms (246A, 246B) are pivotally connected.

Abstract: This application describes a system that captures 3D geometry commands from a first 3D graphics process and stores them in a shared memory. A second 3D environment process creates a 3D display environment using a display and display hardware. A third process obtains the 3D commands and supplies them to the hardware to place 3D objects in the 3D environment. The result is a fused display environment where 3D objects are displayed along with other display elements. Input events in the environment are analyzed and mapped to the 3D graphics process or the environment where they affect corresponding processing.

Abstract: A method and system for detecting and correcting a bad bit error in a solid-state nonvolatile memory device. The device includes a bad bit detection module that receives an old page from the memory device and determines whether a page has a bad bit. The device further includes a bad bit correction module that generates a new page, determines a location of the bad bit, determines a preferred value of the bad bit, determines a user value of the bad bit and inserts the preferred value into a string of bits corresponding to substantive data of the old page, recording the string of bits with the preferred value inserted therein and stores the new page at an address of the old page.

Abstract: The present invention is a system that grids original data, maps the data at the grid locations to height values at corresponding landscape image pixel locations and renders the landscape pixels into a three-dimensional (3D) landscape image. The landscape pixels can have arbitrary shapes and can be augmented with additional 3D information from the original data, such as an offset providing additional information, or generated from processing of the original data, such as to alert when a threshold is exceeded, or added for other purposes such as to point out a feature. The pixels can also convey additional information from the original data using other pixel characteristics such as texture, color, transparency, etc.

Abstract: A system may include a device that is in a first location that is not readily accessible. The device may detect a powering up of the device a particular quantity of times during a particular time interval. Powering up of the device may be controlled from a second location that is readily accessible. The device may also be reset, in response to detecting the device being powered up the particular quantity of times during the particular time interval, to original factory settings.

Abstract: A method and apparatus for utilizing a higher-level cache as a neighbor cache directory in a multi-processor system are provided. In the method and apparatus, when the data field of a portion or all of the cache is unused, a remaining portion of the cache is repurposed for usage as neighbor cache directory. The neighbor cache provides a pointer to another cache in the multi-processor system storing memory data. The neighbor cache directory can be searched in the same manner as a data cache.

Abstract: A multi-chip module configuration includes two processors, each having two nodes, each node including multiple cores or compute units. Each node is connected to the other nodes by links that are high bandwidth or low bandwidth. Routing of traffic between the nodes is controlled at each node according to a routing table and/or a control register that optimize bandwidth usage and traffic congestion control.

Abstract: A method and apparatus for accelerated shared data migration between cores is disclosed.

Abstract: A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.

Abstract: A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.

Abstract: A method and apparatus for a selectively bypassing a cache in a processor of a computing device are disclosed.

Abstract: The present invention is a system that receives data in different formats from different devices/applications in the format native to the devices/applications and fuses the data into a common shared audio/video collaborative environment including a composite display showing the data from the different sources in different areas of the display and composite audio. The common environment is presented to users who can be at remote locations. The users are allowed to supply a control input for the different device data sources and the control input is mapped back to the source, thereby controlling the source. The location of the control input on the remote display is mapped to the storage area for that portion of the display and the control data is transmitted to the corresponding device/application.

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.