Patents by Inventor William E. Edwards

William E. Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170091139
    Abstract: A method and apparatus provide an ability to selectively couple one of the output of the buffer or the output of the digital driver to a data terminal based upon a state of a storage location in which a stored first select indicator is stored and based upon a state of a selection signal. An external serial interface, at a semiconductor die, includes the data terminal, a selection terminal to receive the selection signal, and a clock terminal to receive a clock signal. A buffer includes an input to receive a secondary signal and an output to provide the secondary signal to the data terminal. A digital driver includes a digital output coupled to the data terminal. A first storage location has a storage state based upon the stored first select indicator. Select circuitry provides the selectively coupling.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: William E. Edwards, Jesse R. Beeker
  • Patent number: 9601479
    Abstract: A buffer or voltage protection circuit, a circuit including same, and an associated method of operation are disclosed. In one example embodiment, the integrated circuit includes a first input terminal, a first circuit portion having a second input terminal, and a second circuit portion. The second circuit portion includes a transistor device having first, second, and third ports, where the first and second ports are respectively electrically coupled to the first input terminal and second input terminal, respectively. Additionally, the second circuit portion also includes a diode-type device that is electrically coupled between the third port and either a power source or a power input terminal, and a buffer/driver circuit and a capacitor coupled in series between the third and second ports. The second circuit portion operates to prevent the second input terminal from being exposed to an undesirably-high voltage level.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 21, 2017
    Assignee: NXP USA, Inc.
    Inventors: William E. Edwards, John M. Pigott
  • Publication number: 20170016423
    Abstract: A control methodology and apparatus for an engine suitable for use in capacitor discharge ignition systems for internal combustion engines or brushless DC motors is provided, which make use of a simple logic block to determine for instance an ignition timing advance angle or duty cycle signal based on actual engine speed versus engine control parameter data stored in a table, which is a read-only memory, preferably configurable. To minimise memory space, a small number of values of engine control parameter versus engine speed are stored in the table and the logic block determines the required engine control signal for a measured value of engine speed by an interpolation process, preferably linear interpolation.
    Type: Application
    Filed: December 16, 2013
    Publication date: January 19, 2017
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Michael Robert GARRARD, William E. EDWARDS, John Matthew HALL
  • Patent number: 9506979
    Abstract: An integrated circuit having normal and special operating modes includes a mode entry interlock (201) which is enabled by an initialization command and an externally supplied voltage at a first I/O terminal (204) to detect a conflict at the I/O terminal for reducing the likelihood of inadvertent entry into the special operating mode. The mode entry interlock also includes a second I/O terminal (212) for receiving a disassociated software command to enter into the special operating mode, and mode control logic (210, 216) for evaluating the received software command against any detected conflict at the I/O terminal to generate a special operating mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the first logic state.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: November 29, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William E. Edwards, John M. Hall
  • Patent number: 9465075
    Abstract: A method of providing wetting current diagnostics for a load control switch includes changing test switch settings of a detection circuit from an operational configuration to a testing configuration. The test switch settings specify respective states of first and second test switches of the detection circuit. The first and second test switches are connected to a node of the detection circuit through which, in the operational configuration, a wetting current for the load control switch flows. The method includes determining whether a voltage at the node becomes no longer indicative of the operational configuration as a result of the changed test switch settings, returning the test switch settings to the operational configuration, and providing a wetting current fault indication if the voltage at the node fails to return to a level indicative of the operational configuration after returning the test switch settings to the operational configuration.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: October 11, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: William E. Edwards, Anthony F. Andresen
  • Publication number: 20160290253
    Abstract: An ignition control device having an Electronic Fuel Injection mode and a Capacitive Discharge ignition mode is described. The ignition control device comprises: an output for providing an output voltage, connected or connectable to a load, the load being a fuel injection actuator of an EFI system or an ignition capacitor of a CDI system; and a driver unit connected to the output, for driving the output voltage from a low level a high level and from the high level to the low level in dependence on an input signal, each transition of the output voltage from the low level to the high level having a low-to-high transition time which is longer for the CDI mode than for the EFI mode.
    Type: Application
    Filed: November 22, 2013
    Publication date: October 6, 2016
    Inventors: Michael Robert GARRARD, William E. EDWARDS, John Matthew HALL
  • Publication number: 20160282896
    Abstract: A method of undervoltage detection includes detecting a voltage level for a power supply of a system, placing the system in an undervoltage state if the voltage level is below an undervoltage threshold, activating a load of the system at a first power level if the detected voltage level exceeds a first activation threshold and if the system resides in the undervoltage state, and activating the load at a second power level if the detected voltage level exceeds a second activation threshold.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: William E. Edwards, Anthony F. Andresen
  • Patent number: 9435277
    Abstract: The present application provides a calibration device for calibrating a crank angle of a calibrateable combustion engine, the calibrateable combustion engine and a method for calibrating. The calibration device is provided to determine a trigger wheel angle offset from a combustionless driving of the combustion engine in that an in-cylinder pressure profile is recorded, on the basis of which a trigger wheel angle offset is determined and stored at an offset memory of the combustion engine. The combustion engine is configured to determine a crank angle on the basis of a measured trigger wheel angle and the stored trigger wheel angle offset.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: September 6, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Robert Garrard, William E. Edwards, Alistair Paul Robertson
  • Publication number: 20160238658
    Abstract: A circuit for diagnostic testing includes a current source coupled to a power source and configured to provide wetting current along a path to a load control switch, a current sensor connected in series with the current source along the path, the current sensor being configured to generate a current sensor signal indicative of a current level along the path, a voltage measurement unit having an input terminal coupled to a node along the path through which the wetting current flows to reach the load control switch, the voltage measurement unit being configured to detect a state of the load control switch based on a voltage at the node, and a controller coupled to the current sensor and the voltage measurement unit, the controller being configured to determine a wetting current diagnostic condition in accordance with the current level and the detected state.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 18, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: William E. Edwards, Randall C. Gray, Anthony F. Andresen
  • Patent number: 9397082
    Abstract: First and second semiconductor die are mounted to first and second die pads of a lead frame disposed in a lead frame sheet. With a plurality of wire bonds, each post of a plurality of posts of the lead frame is connected to the first and second semiconductor die. Each post extends inward from opposite sides of the lead frame between the first and second die pads and is connected with a respective one of a plurality of leads of the lead frame. The first and second semiconductor die, the plurality of posts of the lead frame, and the plurality of wire bonds are encapsulated in a package. The lead frame sheet is sheared to define each lead of the plurality of leads. The plurality of posts includes first and second sets of posts extending inward from first and second opposite sides of the lead frame.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: July 19, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: William E. Edwards, Gary C. Johnson
  • Publication number: 20160195454
    Abstract: A system for determining a temperature of a first portion of an engine, and related circuit, and related method of operation, are disclosed. In one example embodiment, the system includes a wheel having a plurality of magnetic teeth, and an electrical circuit including a variable reluctance sensor (VRS) including at least one winding, the VRS being positioned proximate the wheel, where the VRS is in thermal contact with the first portion, and a comparator having first and second input terminals and an output terminal, where the comparator is configured to output an output signal at the output terminal. Either the output signal or a further signal generated by the electrical circuit is at least indirectly indicative of a resistance of the at least one winding, whereby an indication of the temperature of the first portion can be determined based upon the output signal or further signal.
    Type: Application
    Filed: January 2, 2015
    Publication date: July 7, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: William E. Edwards, Michael R. Garrard
  • Publication number: 20160182033
    Abstract: Systems, methods, and circuits for determining or more statuses are disclosed herein. In one example embodiment, such a system includes a first port configured to be coupled to a switch, a capacitor, a comparator having first and second input ports and an output port, a currant source coupled to the first input port, and a control component. The first input port is coupled to the first port and a threshold voltage is applied to the second input port. The control component is configured so that, in at least one circumstance, it causes the current source to cease driving the current in response to receiving an indication from the output post indicating that an additional voltage applied to the first input port has changed from being less than the threshold voltage to being greater than that voltage, the indication being indicative of the switch status.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: William E. Edwards, Anthony F. Andresen
  • Publication number: 20160178672
    Abstract: Systems, methods, and circuits for determining one or more switch statuses are disclosed herein. In one example embodiment, such a system for determining a status of a switch having first and second terminals includes a first port configured to be coupled to the first terminal, a second port configured to be coupled to the second terminal, and a capacitor coupled between the first port and ground. Additionally, the system includes a comparator device having first and second input ports and an output port, the first input post being coupled at least indirectly to the first port, a current source coupled to the first input port, and a voltage source coupled between the second port and the second input port. The comparator device is configured to provide an output signal at the output port that is at least sometimes indicative of the status of the switch.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: William E. Edwards, Anthony F. Andresen
  • Patent number: 9366548
    Abstract: The embodiments described herein include systems with a variable reluctance sensor (VRS) interface and methods of their operation that may reduce the probability of erroneous transitions in a resulting generated detect signal. As such, the VRS interface can improve the accuracy of position and/or motion determinations, and thus can improve the performance of a wide variety of devices that use variable reluctance sensors. In one embodiment the VRS interface uses a comparator with hysteresis to generate a trailing edge signal. In another embodiment the VRS interface uses bias voltages to reduce the probability of erroneous transitions in a trailing edge signal. In either case the VRS interface can prevent erroneous transitions in the detect signal and thus may improve the performance and accuracy of the system.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: June 14, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: William E. Edwards, Mike R. Garrard
  • Publication number: 20160160780
    Abstract: An electronic control unit suitable for a motorcycle provides diagnostic support, tachometer drive and warning lamp drive all multiplexed onto one pin and driven by a single driver circuit. In a diagnostics mode, the pin is connected to diagnostic equipment. When a diagnostic test has been completed, a tachometer drive signal is output on the pin, the drive signal having a duty cycle set high enough to illuminate the warning lamp if a fault condition is detected by on-board sensors. By combining multiple functions onto a single pin with a single driver circuit, the cost of implementing an engine control unit may be reduced compared with existing arrangements which require separate pins and drivers for each function.
    Type: Application
    Filed: July 23, 2013
    Publication date: June 9, 2016
    Applicants: Freescale Semiconductor, Inc., EFI ANALYTICS, INC.
    Inventors: Mike GARRARD, Anoop K. AGGARWAL, William E. EDWARDS, Philip TOBIN
  • Publication number: 20160131713
    Abstract: The embodiments described herein provide systems and methods for determining the health status of a sensed switch. In general, the embodiments described herein determine a measure of a health status of the sensed switch by comparing a voltage on the sensed switch, ascertaining a first comparator state under one test condition and ascertaining a second comparator state under a second test condition. The first comparator state and the second comparator state are and then compared to determine the measure of the health status of the sensed switch.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 12, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: William E. EDWARDS, Anthony F. ANDRESEN, Randall C. GRAY
  • Patent number: 9329237
    Abstract: A method of switch detection is disclosed that comprises, enabling a low power mode on a switch detection device, activating a first detection circuit for detecting, at a first expiration of a first polling time interval, a first switch state of a first switch having a first priority level, the first switch state including one of a first open state and a first closed state, comparing the detected first switch state with a prior first switch state, and activating a second detection circuit for detecting, at a second expiration of a second polling time interval, a second switch state of a second switch having a second priority level, the second switch including one of a second open state and a second closed state, and the second polling time interval being greater than the first polling time interval, and the second priority level being different from the first priority level.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: May 3, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: William E. Edwards, Anthony F. Andresen, Randall C. Gray
  • Publication number: 20160118373
    Abstract: First and second semiconductor die are mounted to first and second die pads of a lead frame disposed in a lead frame sheet. With a plurality of wire bonds, each post of a plurality of posts of the lead frame is connected to the first and second semiconductor die. Each post extends inward from opposite sides of the lead frame between the first and second die pads and is connected with a respective one of a plurality of leads of the lead frame. The first and second semiconductor die, the plurality of posts of the lead frame, and the plurality of wire bonds are encapsulated in a package. The lead frame sheet is sheared to define each lead of the plurality of leads. The plurality of posts includes first and second sets of posts extending inward from first and second opposite sides of the lead frame.
    Type: Application
    Filed: January 7, 2016
    Publication date: April 28, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: William E. Edwards, Gary C. Johnson
  • Patent number: 9322870
    Abstract: A method of testing a semiconductor device includes forming a test circuit over a semiconductor substrate. The test circuit includes a plurality of interconnects electrically connected to a set of device structures supported by the semiconductor substrate. A test, such as a gate stress or leakage current test, of each device structure is conducted with the test circuit. The plurality of interconnects are removed after conducting the test.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: April 26, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William E. Edwards, Randall C. Gray, Christopher B. Lesher
  • Publication number: 20160091908
    Abstract: A circuit includes an evaluation node through which current flows from a voltage source node to a sensed switch when the sensed switch is closed. First and second control switches are disposed between the voltage source node and the evaluation node to switch between first and second current paths for the current. The current passes through the first control switch when flowing along the first current path. The second control switch is coupled to a control terminal of the first control switch to deactivate the first control switch and allow the current to flow through the second current path. Multiple passive circuit elements are configured to establish first and second current levels for the current. The passive circuit elements are disposed between the voltage source node and the evaluation node in a circuit arrangement in which no current path to ground is present when the sensed switch is open.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: William E. Edwards, Anthony F. Andresen