Patents by Inventor William G. Bliss
William G. Bliss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8015477Abstract: An improved Viterbi detector is disclosed in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. Also disclosed is a method of reducing the complexity of the branch metric calculations by clustering branches corresponding to signals with similar signal-dependent noise statistics. A feature of this architecture is that the branch metrics (and their corresponding square difference operators) are clustered into multiple groups, where all the members of each group draw input from a single, shared noise predictive filter corresponding to the group. In recording technologies as practiced today, physical imperfections in the representation of recorded user data in the recording medium itself are becoming the dominate source of noise in the read back data. This noise is highly dependent on what was (intended to be) written in the medium. The disclosed Viterbi detector exploits this statistical dependence of the noise on the signal.Type: GrantFiled: June 21, 2010Date of Patent: September 6, 2011Assignee: Marvell International Ltd.Inventors: Heinrich J. Stockmanns, William G. Bliss, Razmik Karabed, James W. Rae
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Patent number: 7907359Abstract: The invention relates to a data modulation method applicable to make data streams tend to have desired properties, useful for clock recovery, making signals more distinguishable, or enforcing run-length conditions. A stream of input data and a corresponding stream of output data are grouped into elements of a finite field. Input elements of said input data are modified by a transform generating output elements of the output data, such that a current output element is a linear combination of a current input element and at least one previous output element. A multiplier applied to at least one previous output element is a non-zero and non-unity element of the finite field. A set of initial conditions inherent to the transform, is selected such that the output elements resulting from the transform tend to have the desired property.Type: GrantFiled: December 29, 2008Date of Patent: March 15, 2011Assignee: STMicroelectronics, Inc.Inventors: William G. Bliss, Razmik Karabed
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Patent number: 7904795Abstract: A decoder for error correction an encoded message, such as one encoded by a turbo encoder, with reduced iterations due to an improved stopping criterion. The decoder includes an error correction loop that iteratively processes a message that is encoded prior to transmittal over a communication channel. The error correction loop generates, such as with a Reed-Solomon decoder, an error location polynomial in each iterative process. A stopping mechanism in the decoder allows an additional iteration of the message decoding based on the error location polynomial, such as by obtaining the degree of the error location polynomial and comparing it to a threshold. In one example, the threshold is the maximum number of symbol errors correctable by the Reed-Solomon code embodied in the decoder. The stopping mechanism allows additional iterations when the stopping criterion (or polynomial degree) is greater than the maximum number of symbol errors correctable by the Reed-Solomon code.Type: GrantFiled: March 3, 2009Date of Patent: March 8, 2011Assignee: STMicroelectronics, Inc.Inventors: Yu Liao, William G. Bliss, Engling Yeo
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Publication number: 20100322359Abstract: An improved Viterbi detector is disclosed in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. Also disclosed is a method of reducing the complexity of the branch metric calculations by clustering branches corresponding to signals with similar signal-dependent noise statistics. A feature of this architecture is that the branch metrics (and their corresponding square difference operators) are clustered into multiple groups, where all the members of each group draw input from a single, shared noise predictive filter corresponding to the group. In recording technologies as practiced today, physical imperfections in the representation of recorded user data in the recording medium itself are becoming the dominate source of noise in the read back data. This noise is highly dependent on what was (intended to be) written in the medium. The disclosed Viterbi detector exploits this statistical dependence of the noise on the signal.Type: ApplicationFiled: June 21, 2010Publication date: December 23, 2010Inventors: Heinrich J. Stockmanns, William G. Bliss, Razmik Karabed, James W. Rae
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Patent number: 7743314Abstract: An improved Viterbi detector is disclosed in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. Also disclosed is a method of reducing the complexity of the branch metric calculations by clustering branches corresponding to signals with similar signal-dependent noise statistics. A feature of this architecture is that the branch metrics (and their corresponding square difference operators) are clustered into multiple groups, where all the members of each group draw input from a single, shared noise predictive filter corresponding to the group. In recording technologies as practiced today, physical imperfections in the representation of recorded user data in the recording medium itself are becoming the dominate source of noise in the read back data. This noise is highly dependent on what was (intended to be) written in the medium. The disclosed Viterbi detector exploits this statistical dependence of the noise on the signal.Type: GrantFiled: December 1, 2006Date of Patent: June 22, 2010Assignee: Marvell International Ltd.Inventors: Heinrich J. Stockmanns, William G. Bliss, Razmik Karabed, James W. Rae
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Publication number: 20090282320Abstract: A decoder for error correction an encoded message, such as one encoded by a turbo encoder, with reduced iterations due to an improved stopping criterion. The decoder includes an error correction loop that iteratively processes a message that is encoded prior to transmittal over a communication channel. The error correction loop generates, such as with a Reed-Solomon decoder, an error location polynomial in each iterative process. A stopping mechanism in the decoder allows an additional iteration of the message decoding based on the error location polynomial, such as by obtaining the degree of the error location polynomial and comparing it to a threshold. In one example, the threshold is the maximum number of symbol errors correctable by the Reed-Solomon code embodied in the decoder. The stopping mechanism allows additional iterations when the stopping criterion (or polynomial degree) is greater than the maximum number of symbol errors correctable by the Reed-Solomon code.Type: ApplicationFiled: March 3, 2009Publication date: November 12, 2009Applicant: STMicroelectronics, IncInventors: Yu Liao, William G. Bliss, Engling Yeo
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Publication number: 20090168620Abstract: The invention relates to a data modulation method applicable to make data streams tend to have desired properties, useful for clock recovery, making signals more distinguishable, or enforcing run-length conditions. A stream of input data and a corresponding stream of output data are grouped into elements of a finite field. Input elements of said input data are modified by a transform generating output elements of the output data, such that a current output element is a linear combination of a current input element and at least one previous output element. A multiplier applied to at least one previous output element is a non-zero and non-unity element of the finite field. A set of initial conditions inherent to the transform, is selected such that the output elements resulting from the transform tend to have the desired property.Type: ApplicationFiled: December 29, 2008Publication date: July 2, 2009Applicant: STMICROELECTRONICS, INC.Inventors: William G. Bliss, Razmik Karabed
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Patent number: 7486456Abstract: The invention relates to a data modulation method applicable to make data streams tend to have desired properties, useful for clock recovery, making signals more distinguishable, or enforcing run-length conditions. A stream of input data and a corresponding stream of output data are grouped into elements of a finite field. Input elements of said input data are modified by a transform generating output elements of the output data, such that a current output element is a linear combination of a current input element and at least one previous output element. A multiplier applied to at least one previous output element is a non-zero and non-unity element of the finite field. A set of initial conditions inherent to the transform, is selected such that the output elements resulting from the transform tend to have the desired property.Type: GrantFiled: December 17, 2004Date of Patent: February 3, 2009Assignee: STMicroelectronics, Inc.Inventors: William G. Bliss, Razmik Karabed
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Patent number: 7274312Abstract: An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b. . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.Type: GrantFiled: April 6, 2006Date of Patent: September 25, 2007Assignee: Infineon Technologies AGInventors: William G. Bliss, Andrei Vityaev, Razmik Karabed
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Patent number: 7178084Abstract: A data coding method produces codewords with a scheme that changes for different codewords, and decodes codewords with a scheme that remains constant for all codewords. The coding method receives k user bits, codes the user bits to produce k+r output bits, corrupts any one of the output bits, and accurately reproduces at least k?r?1 user bits. Codewords coded using the appropriate initial conditions are output. For each codeword, the appropriate initial conditions are appended to the codeword coded therefrom.Type: GrantFiled: September 25, 2002Date of Patent: February 13, 2007Assignee: Infineon Technologies AGInventors: William G. Bliss, Andrei Vityaev, Razmik Karabed
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Patent number: 7137056Abstract: The present invention relates to a coding system characterized by various combinations of the following properties: 1) Even parity at the output of d of the precoder; 2) A coding rate of 32/34; 3) At least 9 ones per codeword; 4) No more than 13 consecutive zeros in the stream of encoded data (G=13); 5) No more than 13 consecutive zeros in any run of every-other-bit in the stream of codewords (I=13); 6) For closed error events in y or y? having squared-distance?(1 to 1.5)×dmfb2 in the detector, the decoder produces at most 4 corresponding erroneous data bytes; 7) Decoding of a 34 bit codeword may begin when 19 of its bits have been received; 8) If the Viterbi detector 108 outputs Non-Return to Zero (NRZ) symbols, then its output is filtered by (1?D^2) before being decoded, but if the Viterbi detector outputs NRZ Inverter (NRZI) symbols, then its output is decoded directly; and 9) The even parity is on NRZ symbols.Type: GrantFiled: September 25, 2002Date of Patent: November 14, 2006Assignee: Infineon Technologies North America Corp.Inventors: Jonathan Ashley, William G. Bliss, Razmik Karabed, Kaichi Zhang
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Patent number: 7053801Abstract: An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b3 . . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.Type: GrantFiled: June 18, 2004Date of Patent: May 30, 2006Assignee: Infineon Technologies AGInventors: William G. Bliss, Andrei Vityaev, Razmik Karabed
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Patent number: 6819514Abstract: A sampled amplitude read channel for magnetic disk recording which asynchronously samples the analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector is disclosed. To minimize interference from the timing and gain control loops, the phase and magnitude response of the adaptive equalizer filter are constrained at a predetermined frequency using an optimal orthogonal projection operation as a modification to a least mean square (LMS) adaptation algorithm. Further, with interpolated timing recovery, the equalizer filter and its associated latency are removed from the timing recovery loop, thereby allowing a higher order discrete time filter and a lower order analog filter.Type: GrantFiled: April 30, 1996Date of Patent: November 16, 2004Assignee: Cirrus Logic, Inc.Inventors: Richard T. Behrens, Li Du, William G. Bliss, David E. Reed, Mark S. Spurbeck
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Publication number: 20040222905Abstract: An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b3 . . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.Type: ApplicationFiled: June 18, 2004Publication date: November 11, 2004Applicant: Infineon Technologies AGInventors: William G. Bliss, Andrei Vityaey, Razmik Karabed
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Patent number: 6809894Abstract: A method and apparatus for handling end of data processing in a data storage device. The method includes receiving a plurality of user data bits at a write channel. The method further includes appending primary padding bits to user data bits if the plurality of user data bits is less than a multiple of an input block length of an encoder in the write channel and encoding the plurality of user data bits and any primary padding bits into a plurality of encoded data bytes. Additionally, the method includes appending an end of data marker to an end of the plurality of encoded data bytes, wherein the end of data marker has a length of no more than one byte, and writing the plurality of encoded data bytes and the end of data marker to the data store.Type: GrantFiled: June 29, 2001Date of Patent: October 26, 2004Assignee: Infineon Technologies AGInventors: William G. Bliss, Razmik Karabed, James W. Rae, Heiner Stockmanns, Kaichi Zhang
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Patent number: 6788482Abstract: A method and apparatus for Viterbi detector state metric re-normalization. The method includes fabricating a Viterbi detector (138) having a predetermined number of states, wherein the Viterbi detector (138) stores a state metric value and a branch metric value for each state, and wherein the Viterbi detector (138) implements a trellis diagram. The method includes constructing a Viterbi detector (138) which can support a state metric value having g+h′ number of bits. The number of bits needed to represent the branch metric value is represented by (g) and the additional number of bits needed to represent the state metric value is represented by (h′). The additional number of bits (h′) is less than the additional number of bits (h) determined using the following inequality: 2h−1−h≧K−1, wherein K represent the constraint length of the trellis diagram.Type: GrantFiled: June 29, 2001Date of Patent: September 7, 2004Assignee: Infineon Technologies AGInventors: William G. Bliss, Razmik Karabed, James W. Rae, Heiner Stockmanns
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Patent number: 6788223Abstract: An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b3 . . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.Type: GrantFiled: September 25, 2002Date of Patent: September 7, 2004Assignee: Infineon Technolgies NA Corp.Inventors: William G. Bliss, Andrei Vityaev, Razmik Karabed
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Patent number: 6774825Abstract: A system and method to modulate coding based on an ECC interleave structure include a first encoder encoding an input stream of bits comprising input blocks sorted into interleaves. A second encoder encodes a subset of the input blocks to produce output blocks, where the first encoder permutates a remainder of the input blocks and the output blocks to produce a codeword.Type: GrantFiled: September 25, 2002Date of Patent: August 10, 2004Assignee: Infineon Technologies AGInventors: William G. Bliss, Andrei Vityaev, Razmik Karabed, Ali Najafi, Jonathan Ashley
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Patent number: 6771442Abstract: An apparatus and method for adding errors to magnetic data and then detecting the errors is revealed. The method includes providing a magnetic recording channel, reading and digitizing a stored signal, introducing an error signal that emulates off-track interference, adding the error to the digitized signal, and determining an error rate. The apparatus includes a magnetic recording channel having a linear feedback shift register to generate a pseudo-random binary sequence, circuitry to convert the sequence into an error signal, and a Viterbi detector to quantify an error rate.Type: GrantFiled: June 29, 2001Date of Patent: August 3, 2004Assignee: Infineon Technologies AGInventors: William G. Bliss, James W. Rae
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Patent number: 6753797Abstract: A coding system that in a first embodiment is capable of encoding 16-bit input words into even parity 17-bit codewords, wherein the codewords have at least 7 ones, wherein the codewords has an 8-bit first half and a 9-bit second half, wherein the first half has at least 3 or more ones, and wherein the second half comprises at least 3 or more ones. The first half and second half of the codewords each have odd-coordinate bits and even-coordinate bits, at least one odd-coordinate bit of each half has a value of one, and at least one even-coordinate bit of each half has a value of one. In a second embodiment, the coding system is capable of encoding 16-bit input words into even parity 17-bit codewords, wherein the codewords have at least 7 ones, wherein the codewords have an 11-bit first half and a 6-bit second half, wherein the first half comprises at least 3 or more ones, and wherein the second half has at least 2 or more ones.Type: GrantFiled: September 25, 2002Date of Patent: June 22, 2004Assignee: Infineon Technologies AGInventors: William G. Bliss, Razmik Karabed