Patents by Inventor William Henry Radke
William Henry Radke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8631302Abstract: Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules. In selected examples, memory blocks and associated error correction code are mixed between multiple levels of memory device hierarchy.Type: GrantFiled: January 21, 2013Date of Patent: January 14, 2014Assignee: Micron Technology, Inc.Inventor: William Henry Radke
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Patent number: 8560735Abstract: Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.Type: GrantFiled: August 15, 2008Date of Patent: October 15, 2013Assignee: Micron Technology, Inc.Inventors: Victor Tsai, William Henry Radke, Bob Leibowitz
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Publication number: 20130254630Abstract: Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Additional embodiments may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additional embodiments may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.Type: ApplicationFiled: May 29, 2013Publication date: September 26, 2013Applicant: Micron Technology, Inc.Inventors: Michael Murray, William Henry Radke
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Publication number: 20130238958Abstract: Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.Type: ApplicationFiled: March 6, 2012Publication date: September 12, 2013Inventor: William Henry Radke
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Patent number: 8458564Abstract: Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Methods, apparatus, systems, and data structures may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additionally, various methods, apparatus, systems, and data structures may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.Type: GrantFiled: December 22, 2010Date of Patent: June 4, 2013Assignee: Micron Technology, Inc.Inventors: Michael Murray, William Henry Radke
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Publication number: 20130058164Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.Type: ApplicationFiled: July 31, 2012Publication date: March 7, 2013Inventors: Violante Moschiano, Tommaso Vali, Giovanni Naso, Vishal Sarin, William Henry Radke, Theodore T. Pekny
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Publication number: 20130051141Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.Type: ApplicationFiled: August 26, 2011Publication date: February 28, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Tommaso Vali, Giovanni Naso, Vishal Sarin, William Henry Radke, Theodore T. Pekny
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Patent number: 8359514Abstract: Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules. In selected examples, memory blocks and associated error correction code are mixed between multiple levels of memory device hierarchy.Type: GrantFiled: August 15, 2008Date of Patent: January 22, 2013Assignee: Micron Technology, Inc.Inventor: William Henry Radke
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Patent number: 8356216Abstract: Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.Type: GrantFiled: January 9, 2012Date of Patent: January 15, 2013Assignee: Micron Technology, Inc.Inventors: William Henry Radke, Peter Sean Feeley, Siamack Nemazie
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Patent number: 8331143Abstract: A memory device is described that provides increased output data to help evaluate data errors from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data.Type: GrantFiled: July 25, 2011Date of Patent: December 11, 2012Assignee: Micron Technology, Inc.Inventor: William Henry Radke
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Patent number: 8189387Abstract: A memory device is described that comprises determining which read data state of more than 2X read data states a memory cell is in after the memory cell has been programmed to one of 2X program data states, wherein the determined read data state corresponds to X digits of read data and at least one digit of error data, and wherein X is a positive integer.Type: GrantFiled: May 28, 2010Date of Patent: May 29, 2012Assignee: Micron Technology, Inc.Inventor: William Henry Radke
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Publication number: 20120110399Abstract: Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.Type: ApplicationFiled: January 9, 2012Publication date: May 3, 2012Inventors: William Henry Radke, Peter Sean Feeley, Siamack Nemazie
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Patent number: 8095835Abstract: Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.Type: GrantFiled: July 29, 2010Date of Patent: January 10, 2012Assignee: Micron Technology, Inc.Inventors: William Henry Radke, Peter Sean Feeley, Siamack Nemazie
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Publication number: 20110280080Abstract: A memory device is described that provides increased output data to help evaluate data errors from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data.Type: ApplicationFiled: July 25, 2011Publication date: November 17, 2011Inventor: William Henry Radke
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Patent number: 7996727Abstract: Methods and devices operate to apply and provide differing levels of error correction within a multi-level, non-volatile memory. In an example, the differing level of error correction is provided within one page of a row of multi-level cells relative to other pages stored within the same row of multi-level cells.Type: GrantFiled: June 25, 2010Date of Patent: August 9, 2011Assignee: Micron Technology, Inc.Inventor: William Henry Radke
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Patent number: 7990763Abstract: A memory device provides increased output data to help evaluate data errors arising from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data.Type: GrantFiled: November 7, 2008Date of Patent: August 2, 2011Assignee: Micron Technology, Inc.Inventor: William Henry Radke
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Publication number: 20110093766Abstract: Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Methods, apparatus, systems, and data structures may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additionally, various methods, apparatus, systems, and data structures may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.Type: ApplicationFiled: December 22, 2010Publication date: April 21, 2011Inventors: Michael Murray, William Henry Radke
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Patent number: 7861139Abstract: Methods, apparatus, systems, and data structures may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combining a block management data with the particular sector to generate a modified sector. Additionally, various methods, apparatus, systems, and data structures may operate to generate or store error correction data for the modified sector and combining the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.Type: GrantFiled: January 26, 2007Date of Patent: December 28, 2010Assignee: Micron Technology, Inc.Inventors: Michael Murray, William Henry Radke
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Publication number: 20100313077Abstract: Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.Type: ApplicationFiled: July 29, 2010Publication date: December 9, 2010Inventors: William Henry Radke, Peter Sean Feeley, Siamack Nemazie
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Publication number: 20100262890Abstract: Methods and devices operate to apply and provide differing levels of error correction within a multi-level, non-volatile memory. In an example, the differing level of error correction is provided within one page of a row of multi-level cells relative to other pages stored within the same row of multi-level cells.Type: ApplicationFiled: June 25, 2010Publication date: October 14, 2010Inventor: William Henry Radke