Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.

Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive configuration information identifying a set of possible paging occasions and a set of connected mode communications. The UE may receive paging in a paging occasion, of the set of possible paging occasions, for which there is not a collision between the paging occasion and the set of connected mode communications and that is selected from the set of possible paging occasions based at least in part on a power utilization characteristic. Numerous other aspects are described.

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.

Abstract: An integrated circuit includes laterally adjacent first and second devices. The first device includes a first source or drain region, a first gate structure, and a first inner spacer between the first source or drain region and the first gate structure. The second device includes a second source or drain region, a second gate structure, and a second inner spacer between the second source or drain region and the second gate structure. In an example, the first source or drain region has a width that is at least 1 nanometer different from a width of the second source or drain region, and/or the first inner spacer has a width that is at least 1 nanometer different from a width of the second inner spacer.

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.

Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.

Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.

Abstract: One aspect of the present disclosure relates to a system for treating a medical condition in a patient. The system can include a neurostimulator that is in electrical communication with a remote transducer. The neurostimulator can be sized and dimensioned for injection or insertion into a pterygopalatine fossa (PPF) of a patient. The remote transducer, when activated and brought into close proximity to the patient's head, can cause the neurostimulator to deliver an electrical signal to a target neural structure located within the PPF to treat the medical condition.

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

Abstract: A computer implemented method for determining target data for artificial intelligence is disclosed. In one aspect, the method may include identifying an indication of a target state of a first industrial process or asset, and/or of a second industrial process or asset operatively associated with the first industrial process or asset, and determining target data, based on the identified indication of the target state. The identification of the indication of the target state may be based on first monitoring data indicative of data output from first monitoring data source(s) associated with the first industrial process or asset or with the second industrial process or asset. The target data may be determined from second monitoring data indicative of data output from second monitoring data source(s) associated with the first industrial process or asset.

Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

Abstract: Methods and systems for improving headache pain by using feedback mechanisms are provided.

Abstract: Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.