Abstract: The present invention is directed to the field of semiconductor processing and, more particularly, to a method of planarizing or polishing process layers formed above a surface of a semiconducting substrate. In one illustrative embodiment, the method comprises determining the thickness of a process layer formed above a semiconducting substrate and determining a polishing recipe for said process layer based upon the measured thickness of said process layer.

Abstract: A system and method of controlling multi-process, multi-product semiconductor fabrication tools. Individual, grouped, or composite controllers are designated to control various tool operations. First control parameters for a fabrication tool process are generated, where the first control parameters are based on first tool operation attributes. Second control parameters for the process are generated based on second tool operation attributes. The fabrication tool is then controlled by generating cooperative control parameters which are a function of the first and second control parameters. Disturbance information can be shared between controllers for use in generating the first and second control parameters while taking into account disturbance information already discovered and quantified.

Abstract: A system and method for controlling a polishing tool having multiple arms is provided. In accordance with one embodiment, a first removal rate for each arm based on a first wafer run is determined. A downforce adjustment input for each arm is then determined based on a process model, for the arms, which relates a removal rate for a given arm to downforce adjustments on each of the arms and using each first removal rate. The downforce adjustment input for each arm is provided to the polishing tool for polishing a subsequent run. In this manner, the method takes into account each arms removal rate dependency on the downforce adjustments for all of the arms. This can provide reduced removal rate variations between arms as well as between wafer lots and improve the characteristics of the ultimately formed semiconductor devices.