Patents by Inventor William K. Waller

William K. Waller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6574156
    Abstract: A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: June 3, 2003
    Assignee: Micron Technology, Inc.
    Inventors: William K. Waller, Huy T. Vo
  • Publication number: 20020190707
    Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.
    Type: Application
    Filed: August 13, 2002
    Publication date: December 19, 2002
    Inventors: Warren M. Farnworth, William K. Waller, Leland R. Nevill, Raymond J. Beffa, Eugene H. Cloud
  • Publication number: 20020186606
    Abstract: A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the subarrays that is arranged in an order complementary to that of the activated redundant row.
    Type: Application
    Filed: August 5, 2002
    Publication date: December 12, 2002
    Inventors: William K. Waller, Huy T. Vo
  • Patent number: 6477662
    Abstract: An on-chip testing device separately locates must-repairs or preferred-repairs in a row direction and column direction of a memory array. A row counter and a column counter are operated to index the memory array in row-major order, and then in column-major order (or vice versa). A running total of the number of failures is kept for each row and column, when the running total equals or exceeds a predetermined value, the row or column is determined to be a must-repair or a preferred repair. Rows to be repaired are substituted with redundant memory rows and columns to be prepared are substituted with redundant memory columns.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: November 5, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Ray J. Beffa, William K. Waller, Lee R. Nevill, Warren M. Farnworth, Eugene H. Cloud
  • Patent number: 6452415
    Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: September 17, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, William K. Waller, Leland R. Nevill, Raymond J. Beffa, Eugene H. Cloud
  • Patent number: 6442719
    Abstract: A method for identifying intercell defects in a memory device activates a plurality of spaced-apart rows simultaneously. Each of the rows includes cells that are written to logic states corresponding to high voltages. Cells in rows adjacent to the activated rows are written to logic states corresponding to low voltages. After the rows are activated, a testing interval passes to allow charge from cells of the activated rows to leak to adjacent cells through any stringers or other defects. In a device according to the invention, a variable voltage level circuit is incorporated in a precharge and equalization circuit to allow both inverting and non-inverting digit lines of the memory array to be set at the same voltage levels. Because the inverting and non-inverting digit lines are held at the same voltage levels, the number of word lines that can be activated for testing is increased, thereby reducing the overall time for testing.
    Type: Grant
    Filed: May 16, 2000
    Date of Patent: August 27, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Ray Beffa, William K. Waller
  • Patent number: 6434066
    Abstract: A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: August 13, 2002
    Assignee: Micron Technology, Inc.
    Inventors: William K. Waller, Huy T. Vo
  • Patent number: 6430094
    Abstract: A memory device having two or more memory arrays and a testpath operatively connected to one of the memory arrays and not operatively connected to another of the memory arrays at substantially the same time. The memory device may include multiplexers and sense amplifiers to connect the datapath to the memory arrays. The memory device may also include a datapath connected to two or more memory arrays at the same time through multiplexers and sense amplifiers. The memory array may also be embodied as a memory system, including a processor, control logic, and the memory device. A method of operating a testpath of the memory device includes generating control signals to operatively connect the testpath to one of the memory arrays, and not to connect the testpath to another of the memory arrays at substantially the same time.
    Type: Grant
    Filed: May 16, 2000
    Date of Patent: August 6, 2002
    Assignee: Micron Technology, Inc.
    Inventor: William K. Waller
  • Publication number: 20020048199
    Abstract: A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row.
    Type: Application
    Filed: August 28, 2001
    Publication date: April 25, 2002
    Inventors: William K. Waller, Huy T. Vo
  • Publication number: 20020030507
    Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the shortcircuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 14, 2002
    Inventors: Warren M. Farnworth, William K. Waller, Leland R. Nevill, Raymond J. Beffa, Eugene H. Cloud
  • Patent number: 6313658
    Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: November 6, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, William K. Waller, Leland R. Nevill, Raymond J. Beffa, Eugene H. Cloud
  • Patent number: 6310804
    Abstract: A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row. By activating a redundant row in one sub-array and disabling the corresponding redundant row in an adjacent sub-array, the architecture allows for repairs to be conducted in the one sub-array while a good row in the adjacent sub-array is allowed to continue in operation.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: October 30, 2001
    Assignee: Micron Technology, Inc.
    Inventors: William K. Waller, Huy T. Vo
  • Patent number: 6236614
    Abstract: A Dynamic Random Access Memory (DRAM) eliminates the need to route section signals to local phase drivers to generate local phase signals by gating local isolation signals and global phase signals together in the local phase drivers to generate the local phase signals. As a result, the die “footprint” of the DRAM is reduced.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: May 22, 2001
    Assignee: Micron Technology, Inc.
    Inventor: William K. Waller
  • Patent number: 6233185
    Abstract: A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: May 15, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Ray Beffa, Leland R. Nevill, Warren M. Farnworth, Eugene H. Cloud, William K. Waller
  • Patent number: 6145092
    Abstract: An on-chip testing device separately locates must-repairs or preferred-repairs in a row direction and column direction of a memory array. A row counter and a column counter are operated to index the memory array in row-major order, and then in column-major order (or vice versa). A running total of the number of failures is kept for each row and column, when the running total equals or exceeds a predetermined value, the row or column is determined to be a must-repair or a preferred repair. Rows to be repaired are substituted with redundant memory rows and-columns-to be prepared are substituted with redundant memory columns.
    Type: Grant
    Filed: August 23, 1999
    Date of Patent: November 7, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Ray J. Beffa, William K. Waller, Lee R. Nevill, Warren M. Farnworth, Eugene H. Cloud
  • Patent number: 6134160
    Abstract: An architecture for a high-capacity high-speed semiconductor memory device is disclosed. The semiconductor memory device includes memory cell arrays (406) having local word lines and bit lines. The memory cell arrays (406) are further arranged into array groups (402a-402d and 404a-404d). The local word lines (410a-410d) of the memory cell arrays of the same group are commonly connected to global word lines (408). The array groups (402a-402d and 404a-404d) provide data access paths to their respective memory cells by sets of input/output (I/O) lines (416a-416d and 420a-420d). The I/O line sets (416a-416d and 420a-420d) are coupled to data amplifiers by interarray multiplexers (MUXs) (422a-422d). The interarray MUXs (422a-422d) enable defective global word lines of one array group to be replaced by redundant global word lines of an adjacent array group.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: October 17, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: William K. Waller, Kuo-Yuan Hsu
  • Patent number: 6125067
    Abstract: A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row. By activating a redundant row in one sub-array and disabling the corresponding redundant row in an adjacent sub-array, the architecture allows for repairs to be conducted in the one sub-array while a good row in the adjacent sub-array is allowed to continue in operation.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: September 26, 2000
    Assignee: Micron Technology, Inc.
    Inventors: William K. Waller, Huy T. Vo
  • Patent number: 6104661
    Abstract: A Dynamic Random Access Memory (DRAM) eliminates the need to route section signals to local phase drivers to generate local phase signals by gating local isolation signals and global phase signals together in the local phase drivers to generate the local phase signals. As a result, the die "footprint" of the DRAM is reduced.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: August 15, 2000
    Assignee: Micron Technology, Inc.
    Inventor: William K. Waller
  • Patent number: 6081467
    Abstract: A memory device having two or more memory arrays and a testpath operatively connected to one of the memory arrays and not operatively connected to another of the memory arrays at substantially the same time. The memory device may include multiplexers and sense amplifiers to connect the datapath to the memory arrays. The memory device may also include a datapath connected to two or more memory arrays at the same time through multiplexers and sense amplifiers. The memory array may also be embodied as a memory system, including a processor, control logic, and the memory device. A method of operating a testpath of the memory device includes generating control signals to operatively connect the testpath to one of the memory arrays, and not to connect the testpath to another of the memory arrays at substantially the same time.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: June 27, 2000
    Assignee: Micron Technology, Inc.
    Inventor: William K. Waller
  • Patent number: 6079037
    Abstract: A method for identifying intercell defects in a memory device activates a plurality of spaced-apart rows simultaneously. Each of the rows includes cells that are written to logic states corresponding to high voltages. Cells in rows adjacent to the activated rows are written to logic states corresponding to low voltages. After the rows are activated, a testing interval passes to allow charge from cells of the activated rows to leak to adjacent cells through any stringers or other defects. In a device according to the invention, a variable voltage level circuit is incorporated in a precharge and equalization circuit to allow both inverting and non-inverting digit lines of the memory array to be set at the same voltage levels. Because the inverting and non-inverting digit lines are held at the same voltage levels, the number of word lines that can be activated for testing is increased, thereby reducing the overall time for testing.
    Type: Grant
    Filed: August 20, 1997
    Date of Patent: June 20, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Ray Beffa, William K. Waller