Patents by Inventor William N. Thompson
William N. Thompson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6445259Abstract: A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.Type: GrantFiled: August 14, 2001Date of Patent: September 3, 2002Assignee: Micron Technology, Inc.Inventors: William N. Thompson, John D. Porter, Larren Gene Weber
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Patent number: 6384714Abstract: A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.Type: GrantFiled: August 6, 2001Date of Patent: May 7, 2002Assignee: Micron Technology, Inc.Inventors: William N. Thompson, John D. Porter, Larren Gene Weber
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Patent number: 6376297Abstract: An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.Type: GrantFiled: August 5, 1999Date of Patent: April 23, 2002Assignee: Micron Technology, Inc.Inventors: John D. Porter, William N. Thompson
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Publication number: 20020027480Abstract: A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.Type: ApplicationFiled: August 14, 2001Publication date: March 7, 2002Applicant: Micron Technology, Inc.Inventors: William N. Thompson, John D. Porter, Larren Gene Weber
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Publication number: 20020024360Abstract: A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.Type: ApplicationFiled: May 7, 2001Publication date: February 28, 2002Inventors: John D. Porter, Larren G. Weber, William N. Thompson
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Publication number: 20020017965Abstract: A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.Type: ApplicationFiled: August 14, 2001Publication date: February 14, 2002Applicant: Micron Technology, Inc.Inventors: William N. Thompson, John D. Porter, Larren Gene Weber
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Publication number: 20020015335Abstract: An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.Type: ApplicationFiled: December 18, 2000Publication date: February 7, 2002Inventors: John D. Porter, William N. Thompson
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Publication number: 20020012416Abstract: A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.Type: ApplicationFiled: August 6, 2001Publication date: January 31, 2002Applicant: Micron Technology, Inc.Inventors: William N. Thompson, John D. Porter, Larren Gene Weber
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Publication number: 20020000891Abstract: A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.Type: ApplicationFiled: June 25, 2001Publication date: January 3, 2002Applicant: Micron Technology, Inc.Inventors: William N. Thompson, John D. Porter, Larren Gene Weber
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Patent number: 6310820Abstract: A memory device provides a relaxed write timing scheme that improves access time. The address and/or the data is set up to the memory array during a previous write cycle so that the next write cycle can proceed without delays produced in delivering the address and/or the data to the array during the write cycle in which the data is to be written to the array.Type: GrantFiled: June 17, 1999Date of Patent: October 30, 2001Assignee: Micron Technology, Inc.Inventors: John D. Porter, William N. Thompson, Larren G. Weber
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Patent number: 6301188Abstract: A synchronous circuit, such as an SRAM, includes core circuitry for processing input signals and multiple terminals for receiving, respectively, an input signal, an external clock signal and a control signal. The synchronous circuit includes a latch for receiving the input signal and an internal clock signal. The latch has an output connected to the core circuitry and can operate in a latched state and an unlatched state. The circuit also includes an internal clock controller for receiving the external clock signal and the control signal and for providing the internal clock signal to the latch to control transitions of the latch between the latched and unlatched states based on the external clock signal and the control signal.Type: GrantFiled: August 11, 1999Date of Patent: October 9, 2001Assignee: Micron Technology, Inc.Inventors: Larren G. Weber, William N. Thompson, John D. Porter
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Patent number: 6275119Abstract: A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.Type: GrantFiled: August 25, 1999Date of Patent: August 14, 2001Assignee: Micron Technology, Inc.Inventors: William N. Thompson, John D. Porter, Larren Gene Weber
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Patent number: 6239618Abstract: A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.Type: GrantFiled: March 7, 2000Date of Patent: May 29, 2001Assignee: Micron Technology, Inc.Inventors: John D. Porter, Larren G. Weber, William N. Thompson
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Patent number: 6128244Abstract: The invention provides a memory access system and method of operation particularly useful with electronic storage devices having two or more memory units. Accessing of the memory units occurs one at a time and takes place using shared resources, such as shared row and column decoders. In a preferred embodiment, the invention permits the parallel reading of data from one memory unit of a plurality of memory units during a single system clock cycle using shared resources to perform addressing (e.g., read or write access) for the memory unit. The same shared resources are then used by any one of the other memory units during a subsequent system clock cycle to perform its own access function. By reading (or writing) data from (or to) one memory unit only during a single system clock cycle, the shared row and column decoders (and their attendant address lines) become available in a subsequent system clock cycle for use by another memory unit.Type: GrantFiled: June 4, 1998Date of Patent: October 3, 2000Assignee: Micron Technology, Inc.Inventors: William N. Thompson, J. David Porter, Larren G. Weber, John Wilford, Tom Pawlowski
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Patent number: 6088278Abstract: An apparatus and method for sensing the logical state stored in a memory cell includes a pre-amplifier and a latching sense amplifier. The pre-amplifier receives differential signals from a memory array, shifts the signals and amplifies the differential sufficiently for input to the latching sense amplifier. The gain realized through the pre-amplifier facilitates faster and more reliable sensing of the memory cell state. A method comprises receiving first and second signals representative of a logical state stored in a memory cell, pre-amplifying a difference between the first and second signals to produce third and fourth signals having a greater difference, and amplifying the greater difference to more quickly and reliably produce an output indicative of the logical state stored in the memory cell.Type: GrantFiled: July 23, 1998Date of Patent: July 11, 2000Assignee: Micron Technology, Inc.Inventors: John D. Porter, William N. Thompson
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Patent number: 6040713Abstract: A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.Type: GrantFiled: April 22, 1998Date of Patent: March 21, 2000Assignee: Micron Technology, Inc.Inventors: John D. Porter, Larren G. Weber, William N. Thompson
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Patent number: 6026031Abstract: A memory device provides a relaxed write timing scheme that improves access time. The address and/or the data is set up to the memory array during a previous write cycle so that the next write cycle can proceed without delays produced in delivering the address and/or the data to the array during the write cycle in which the data is to be written to the array.Type: GrantFiled: May 13, 1998Date of Patent: February 15, 2000Assignee: Micron Technology, Inc.Inventors: John D. Porter, William N. Thompson, Larren G. Weber
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Patent number: 6005797Abstract: An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to V.sub.cc through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.Type: GrantFiled: March 20, 1998Date of Patent: December 21, 1999Assignee: Micron Technology, Inc.Inventors: John D. Porter, William N. Thompson