Patents by Inventor William Radke
William Radke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150134880Abstract: Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. In certain example embodiments, an active/active fault-tolerant storage device comprising two or more controllers may be implemented. In one aspect, each controller may have two or more processing entities for distributing the processing of the I/O requests. In one embodiment, the configuration of the components, modules and the controller board may be arranged in a manner to enhance heat dissipation, reduce power consumption, spread the power and work load, and reduce latency. In one embodiment, each controller may be coupled to the non-volatile memory (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as the Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium.Type: ApplicationFiled: November 12, 2013Publication date: May 14, 2015Applicant: Skyera, Inc.Inventors: Radoslav Danilak, William Radke
-
Publication number: 20150077922Abstract: A rack mountable 10U storage unit includes a plurality of memory modules arranged in multiple rows. The storage unit also has control circuitry. Each of the memory modules have multiple heating zones and a heat spreader coupled to it. The memory modules may have heat spreaders having differing thermal dissipation capacity coupled to them. The storage unit can accommodate up to 120 memory modules due to a unique method of placing the individual memory modules.Type: ApplicationFiled: July 8, 2014Publication date: March 19, 2015Inventors: Pinchas Herman, William Radke, Radoslav Danilak
-
Publication number: 20140268536Abstract: A rack mountable 1U storage unit includes a plurality of memory modules arranged in two groups. The storage unit also has control circuitry. The memory modules have a dedicated exhaust channel to draw heat away from the memory modules. The exhaust channel for the memory modules is disposed over and is physically separated from the exhaust channel for the control circuitry. The storage unit can accommodate up to 42 memory modules due to a unique method of placing the individual memory modules.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: Skyera, Inc.Inventors: Pinchas Herman, William Radke, Radoslav Danilak
-
Publication number: 20140281177Abstract: Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi-level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.Type: ApplicationFiled: May 30, 2014Publication date: September 18, 2014Applicants: ROUND ROCK RESEARCH, LLCInventors: William Radke, Michael Murray, Martin Ragnar Furuhjelm, John Geldman
-
Publication number: 20140237326Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC).Type: ApplicationFiled: April 4, 2014Publication date: August 21, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Frankie Roohparvar, Vishal Sarin, William Radke
-
Patent number: 8751733Abstract: Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi-level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.Type: GrantFiled: October 22, 2012Date of Patent: June 10, 2014Assignee: Round Rock Research, LLCInventors: William Radke, Michael Murray, Martin Ragnar Furuhjelm, John Geldman
-
Patent number: 8719680Abstract: Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data.Type: GrantFiled: June 27, 2013Date of Patent: May 6, 2014Assignee: Micron Technology, Inc.Inventors: Frankie Roohparvar, Vishal Sarin, William Radke
-
Patent number: 8704840Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.Type: GrantFiled: July 22, 2011Date of Patent: April 22, 2014Assignee: Micron Technology, Inc.Inventor: William Radke
-
Publication number: 20130286745Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC).Type: ApplicationFiled: June 27, 2013Publication date: October 31, 2013Inventors: Frankie Roohparvar, Vishal Sarin, William Radke
-
Patent number: 8499229Abstract: Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can decode error correction codes (ECC).Type: GrantFiled: November 21, 2007Date of Patent: July 30, 2013Assignee: Micro Technology, Inc.Inventors: Frankie Roohparvar, Vishal Sarin, William Radke
-
Patent number: 8446420Abstract: A system for processing graphics data. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.Type: GrantFiled: June 4, 2012Date of Patent: May 21, 2013Assignee: Round Rock Research, LLCInventor: William Radke
-
Publication number: 20120242670Abstract: A system for processing graphics data. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.Type: ApplicationFiled: June 4, 2012Publication date: September 27, 2012Applicant: ROUND ROCK RESEARCH, LLCInventor: William Radke
-
Patent number: 8194086Abstract: A system and method for processing graphics data which requires less read and write bandwidth. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.Type: GrantFiled: March 28, 2011Date of Patent: June 5, 2012Assignee: Round Rock Research, LLCInventor: William Radke
-
Publication number: 20110279465Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.Type: ApplicationFiled: July 22, 2011Publication date: November 17, 2011Applicant: Micron Technology, Inc.Inventor: William Radke
-
Patent number: 7990391Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.Type: GrantFiled: June 13, 2008Date of Patent: August 2, 2011Assignee: Micron Technology, Inc.Inventor: William Radke
-
Publication number: 20110169846Abstract: A system and method for processing graphics data which requires less read and write bandwidth. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.Type: ApplicationFiled: March 28, 2011Publication date: July 14, 2011Applicant: ROUND ROCK RESEARCH, LLCInventor: William Radke
-
Patent number: 7916148Abstract: A system and method for processing graphics data which requires less read and write bandwidth. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.Type: GrantFiled: May 7, 2010Date of Patent: March 29, 2011Assignee: Round Rock Research, LLCInventor: William Radke
-
Publication number: 20100220103Abstract: A system and method for processing graphics data which requires less read and write bandwidth. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.Type: ApplicationFiled: May 7, 2010Publication date: September 2, 2010Applicant: ROUND ROCK RESEARCH, LLCInventor: William Radke
-
Patent number: 7724262Abstract: A system and method for processing graphics data which improves utilization of read and write bandwidth of a graphics processing system. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored in memory page format. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory concurrently with reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to the bank of memory from which the pre-processed data was read. The processing pipeline is capable of concurrently processing an amount of graphics data at least equal to the amount of graphics data included in a page of memory.Type: GrantFiled: May 20, 2008Date of Patent: May 25, 2010Assignee: Round Rock Research, LLCInventor: William Radke
-
Publication number: 20090129169Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC).Type: ApplicationFiled: November 21, 2007Publication date: May 21, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Frankie Roohparvar, Vishal Sarin, William Radke