Abstract: A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memory access request and data may be passed from one memory controller to other memory controller. A memory access request to a memory location in one addressable memory area, but received by a memory controller coupled to another addressable memory area, is passed through the memory controller bus from the receiving memory controller to the memory controller coupled to the addressable memory area in which the requested location is located in order to service the memory access request. Additional memory controllers coupled to a respective addressable memory area may be included in the memory system. The memory controllers are coupled to the memory controller bus in order to receive and pass memory access requests from the other memory controllers.

Abstract: A system and method for processing graphics data which improves utilization of read and write bandwidth of a graphics processing system. The graphics processing system includes an embedded memory array having at least three separate banks of single ported memory in which graphics data are stored in memory page format. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory concurrently with reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to the bank of memory from which the pre-processed data was read. The processing pipeline is capable of concurrently processing an amount of graphics data at least equal to the amount of graphics data included in a page of memory.

Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.

Abstract: A system and method for accessing a memory array where retrieved data is stored in a memory and upon the writing of the data in its modified form, the originally stored data is updated with the modification prior to being written back to the memory array. In this manner, a new error correction code can be calculated prior to writing the data without the need to access the memory array again.

Abstract: A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memory access request and data may be passed from one memory controller to other memory controller. A memory access request to a memory location in one addressable memory area, but received by a memory controller coupled to another addressable memory area, is passed through the memory controller bus from the receiving memory controller to the memory controller coupled to the addressable memory area in which the requested location is located in order to service the memory access request. Additional memory controllers coupled to a respective addressable memory area may be included in the memory system. The memory controllers are coupled to the memory controller bus in order to receive and pass memory access requests from the other memory controllers.

Abstract: A system and method for processing graphics data which improves utilization of read and write bandwidth of a graphics processing system. The graphics processing system includes an embedded memory array having at least three separate banks of single ported memory in which graphics data are stored in memory page format. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory concurrently with reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to the bank of memory from which the pre-processed data was read. The processing pipeline is capable of concurrently processing an amount of graphics data at least equal to the amount of graphics data included in a page of memory.

Abstract: A system and method for accessing a memory array where retrieved data is stored in a memory and upon the writing of the data in its modified form, the originally stored data is updated with the modification prior to being written back to the memory array. In this manner, a new error correction code can be calculated prior to writing the data without the need to access the memory array again.

Abstract: A system and method for storing data in memory in either a packed or unpacked format contiguously and providing retrieved data in an unpacked format. The memory system includes a memory having packed and unpacked data stored in lines of data and a register to store a line of data it receives from the memory. Further included in the system is a selection circuit coupled to receive data from both the memory and the register. The selection circuit selects a portion of data from the lines of data presented to it by the memory and the register to be provided to a data bus according to a select signal provided by a memory address generator. The select signal is calculated by the memory address generator from an expected address at which the data is expected to be located. A second register and a second selection circuit may also be included in the memory system.

Abstract: A memory system and method for allocating and accessing memory. The memory system includes first and second addressable memory regions coupled to a memory controller. The memory controller includes a register to store a respective offset value and values defining portions of the first and second addressable memory regions allocated to first and second logical memory spaces. A first portion of the first addressable memory region is allocated to a first requested memory space, and a second portion of the first addressable memory region is allocated to a second requested memory space. Any remaining portions of the first and second requested memory spaces are remapped to the second addressable memory region.

Abstract: A system and method for accessing a memory array where retrieved data is stored in a memory and upon the writing of the data in its modified form, the originally stored data is updated with the modification prior to being written back to the memory array. In this manner, a new error correction code can be calculated prior to writing the data without the need to access the memory array again.

Abstract: A memory system and method for allocating and accessing memory. The memory system includes first and second addressable memory regions coupled to a memory controller. The memory controller includes a register to store a respective offset value and values defining portions of the first and second addressable memory regions allocated to first and second logical memory spaces. A first portion of the first addressable memory region is allocated to a first requested memory space, and a second portion of the first addressable memory region is allocated to a second requested memory space. Any remaining portions of the first and second requested memory spaces are remapped to the second addressable memory region.