Abstract: A circuit includes multiple switching networks coupled between corresponding multiple RF ports and a common RF port. Each of the multiple switching networks includes a first switch between its corresponding RF port and the common RF port. At least one of the multiple switching networks includes a selectable network between the first switch and the common RF port. The selectable network provides a DC path in a first state and a series capacitance in a second state. A control circuit is configured to establish an RF path by activating a first switch and by deactivating other first switches. The control circuit is also configured to establish an RF path by placing a selectable network in the first state when the control circuit operates in a first mode and by placing a selectable network in the second state when the control circuit operates in a second mode.

Abstract: In accordance with an embodiment, a method of testing an integrated circuit, includes receiving a supply voltage on the integrated circuit via a first input pin, providing power to circuits disposed on the integrated circuit via the first input pin, comparing the supply voltage to an internally generated voltage, generating a digital output value based on the comparing, and applying the digital output value to a pin of the integrated circuit.

Abstract: One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged within the shielding elements. Since at least one partial section of the shielding elements includes a semiconductor material, a shielding device can be realized completely and cost-effectively in an integrated circuit.

Abstract: A standing wave ratio detection arrangement is disclosed. The arrangement includes a standing wave ratio detector and a controller. The standing wave ratio detector is configured to receive an isolated signal and a coupled signal and to generate a multi-bit return loss signal based on the isolated signal and the coupled signal in the analog domain using successive attenuation of the coupled signal. The controller is configured to determine a standing wave ratio from the return loss and to generate an antenna tuner control signal using the standing wave ratio.

Abstract: A CMOS cascode amplifier comprises a cascode circuit comprising a plurality of branches in parallel, each branch comprising a first transistor and a second switchable transistor connected in series forming a cascode pair, wherein the cascode circuit is configured to amplify an input signal. The CMOS cascode amplifier further comprises a bias circuit configured to bias the cascode circuit by providing a bias signal to the first transistor in each of the plurality of the branches in the cascode circuit. In addition, the CMOS cascode amplifier comprises a switching control circuit configured to control a quiescent current in the cascode circuit based on selectively activating the plurality of branches by providing a switching control signal that switches on the second switchable transistor in the one or more activated branches.

Abstract: In accordance with an embodiment, a radio frequency integrated circuit (RFIC) includes an adjustable capacitance coupled to an input terminal of the RFIC, and a first single-pole multiple-throw (SPMT) radio frequency (RF) switch having an input coupled to the adjustable capacitance and a plurality of output nodes coupled to a corresponding plurality of second output terminals of the RFIC.

Abstract: An impedance matching network comprises a first signal terminal configured to receive a signal from a source circuit and a second signal terminal configured to provide the signal to a load circuit. The network further comprises a series branch comprising a variable capacitive component between the first signal terminal and the second signal terminal. The variable capacitive component comprises a plurality of capacitive portions connected in series, wherein at least one of the capacitive portions comprises a switching element comprising a stack of series connected transistors. The impedance matching network also comprises a control component configured to control a capacitance of the variable capacitive component by controlling the at least one of the capacitive portions based on a predetermined algorithm.

Abstract: According to an embodiment, an electrostatic discharge (ESD) protection circuit includes a first transistor having a first source/drain coupled to a first input/output terminal, a second source/drain coupled to a first reference voltage terminal, and a gate coupled to a second reference voltage terminal. The ESD protection circuit further includes a direct current (DC) blocking circuit having a first input/output node coupled to the first input/output terminal, a second input/output node configured to be coupled to a useful circuit, and a third input/output node coupled a gate of the first transistor.

Abstract: A circuit includes a current sensing circuit comprising a current input terminal coupled to an input port, a current output terminal coupled to a transmitted port, and a current sensing output terminal configured to provide a current sensing signal proportional to a current flowing between the current input terminal and the current output terminal. The circuit further includes a voltage sensing circuit having a voltage input terminal coupled to the transmitted port and a voltage sensing output terminal configured to provide a voltage sensing signal proportional to a voltage at the transmitted port. A combining circuit has a first input coupled to the current sensing output terminal, a second input coupled to the voltage sensing output terminal, and a combined output node coupled to an output port.

Abstract: A circuit includes multiple switching networks coupled between corresponding multiple RF ports and a common RF port. Each of the multiple switching networks includes a first switch between its corresponding RF port and the common RF port. At least one of the multiple switching networks includes a selectable network between the first switch and the common RF port. The selectable network provides a DC path in a first state and a series capacitance in a second state. A control circuit is configured to establish an RF path by activating a first switch and by deactivating other first switches. The control circuit is also configured to establish an RF path by placing a selectable network in the first state when the control circuit operates in a first mode and by placing a selectable network in the second state when the control circuit operates in a second mode.

Abstract: In accordance with an embodiment, a method of testing an integrated circuit, includes receiving a supply voltage on the integrated circuit via a first input pin, providing power to circuits disposed on the integrated circuit via the first input pin, comparing the supply voltage to an internally generated voltage, generating a digital output value based on the comparing, and applying the digital output value to a pin of the integrated circuit.

Abstract: In accordance with an embodiment, a switchable capacitance circuit includes a plurality of capacitance-switch cells that each have a capacitance circuit having a capacitance between a first terminal and a second terminal of the capacitance circuit, and a semiconductor switching circuit including a first terminal coupled to the first terminal of the capacitance circuit, a plurality of series connected radio-frequency (RF) switch cells having a load path and a common node. Each of the plurality of series connected RF switch cells has a switch transistor and a gate resistor having a first end coupled to a gate of the switch transistor and a second end coupled to the common node. The switchable capacitance circuit also includes a resistance circuit having a first end coupled to the common node and a second end coupled to a control node.

Abstract: A high-frequency switching circuit includes a high-frequency switching transistor, wherein a high-frequency signal-path extends via a channel-path of the high-frequency switching transistor. The high-frequency switching circuit includes a control circuit and the control circuit is configured to apply at least two different bias potentials to a substrate of the high-frequency switching transistor, depending on a control signal received by the control circuit.

Abstract: In accordance with an embodiment, a method of operating a directional coupler includes determining a coupled power variation by applying an input signal at an input port of the directional coupler, applying a first impedance at a transmitted port of the directional coupler, measuring a first coupled power at a coupled port of the directional coupler after applying the first impedance, applying a second impedance at the transmitted port of the directional coupler, measuring a second coupled power after applying the second impedance, and determining a difference between the first coupled power and the second coupled power to form the coupled power variation.

Abstract: In accordance with an embodiment, a circuit includes a magnetic transformer having a first winding coupled between a first signal node and a second signal node, and a second winding coupled between a first reference node and a current measurement node. A phase shift network is coupled between the second node and a voltage measurement node, and the circuit is configured to indicate an impedance matching condition based on an amplitude difference and a phase difference between the voltage measurement node and the current measurement node.

Abstract: In accordance with an embodiment, a circuit includes a plurality of switching networks coupled between a corresponding plurality of RF ports and a common RF port, and a control circuit. Each of the plurality of switching networks includes a first switch coupled between its corresponding RF port and the common RF port, and at least one of the plurality of switching networks includes a selectable network coupled between the first switch and the common RF port, such that the selectable network provides a DC path in a first state and a series capacitance in a second state.

Abstract: In accordance with an embodiment, a radio frequency (RF) switching circuit includes a plurality of series connected RF switch cells comprising a load path and a control node, a plurality of first gate resistors coupled between control nodes of adjacent RF switch cells, and an input resistor having a first end coupled to a control node of one of the plurality of RF switch cells and a second end configured to an output of a switch driver. Each of the plurality of series connected RF switch cells includes a switch transistor.

Abstract: In accordance with an embodiment, a circuit includes a first signal path coupled between an input port and an output port, and a second coupled between the input port and the output port in parallel with the first signal path. The first signal path includes a low noise amplifier (LNA) having an input node coupled to the input port, and the second signal path includes a switch coupled between the input port and the output port.

Abstract: An impedance matching network comprises a first signal terminal configured to receive a signal from a source circuit and a second signal terminal configured to provide the signal to a load circuit. The network further comprises a series branch comprising a variable capacitive component between the first signal terminal and the second signal terminal. The variable capacitive component comprises a plurality of capacitive portions connected in series, wherein at least one of the capacitive portions comprises a switching element comprising a stack of series connected transistors. The impedance matching network also comprises a control component configured to control a capacitance of the variable capacitive component by controlling the at least one of the capacitive portions based on a predetermined algorithm.

Abstract: A high-frequency switching circuit includes a high-frequency switching transistor, wherein a high-frequency signal-path extends via a channel-path of the high-frequency switching transistor. The high-frequency switching circuit includes a control circuit and the control circuit is configured to apply at least two different bias potentials to a substrate of the high-frequency switching transistor, depending on a control signal received by the control circuit.